diff --git a/board-support/espressif-esp/src/chips/ESP32-C3.svd b/board-support/espressif-esp/src/chips/ESP32-C3.svd index ab064fa93..3d49163c5 100644 --- a/board-support/espressif-esp/src/chips/ESP32-C3.svd +++ b/board-support/espressif-esp/src/chips/ESP32-C3.svd @@ -3,11 +3,10 @@ ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD. ESPRESSIF ESP32-C3 - ESP32-C3 - 8 + ESP32 C-Series + 18 32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE) - - Copyright 2022 Espressif Systems (Shanghai) PTE LTD + Copyright 2024 Espressif Systems (Shanghai) PTE LTD Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -19,15 +18,14 @@ distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and - limitations under the License. - + limitations under the License. RV32IMC r0p0 little false false - 4 + 0 false 32 @@ -351,36 +349,36 @@ - 16 - 0x1 + 4 + 0x4 IV_MEM[%s] The memory that stores initialization vector 0x50 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 H_MEM[%s] The memory that stores GCM hash subkey 0x60 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 J0_MEM[%s] The memory that stores J0 0x70 - 0x8 + 0x20 - 16 - 0x1 + 4 + 0x4 T0_MEM[%s] The memory that stores T0 0x80 - 0x8 + 0x20 DMA_ENABLE @@ -552,7 +550,7 @@ APB_CTRL - Advanced Peripheral Bus Controller + APB (Advanced Peripheral Bus) Controller APB_CTRL 0x60026000 @@ -560,6 +558,10 @@ 0xA0 registers + + APB_CTRL + 14 + SYSCLK_CONF @@ -1057,7 +1059,7 @@ REDCY_SIG0 - APB_CTRL_REDCY_SIG0_REG + APB_CTRL_REDCY_SIG0_REG_REG 0x94 0x20 @@ -1079,7 +1081,7 @@ REDCY_SIG1 - APB_CTRL_REDCY_SIG1_REG + APB_CTRL_REDCY_SIG1_REG_REG 0x98 0x20 @@ -1257,7 +1259,7 @@ PERI_BACKUP_CONFIG - APB_CTRL_PERI_BACKUP_CONFIG_REG + APB_CTRL_PERI_BACKUP_CONFIG_REG_REG 0xB4 0x20 0x00006480 @@ -1315,7 +1317,7 @@ PERI_BACKUP_APB_ADDR - APB_CTRL_PERI_BACKUP_APB_ADDR_REG + APB_CTRL_PERI_BACKUP_APB_ADDR_REG_REG 0xB8 0x20 @@ -1330,7 +1332,7 @@ PERI_BACKUP_MEM_ADDR - APB_CTRL_PERI_BACKUP_MEM_ADDR_REG + APB_CTRL_PERI_BACKUP_MEM_ADDR_REG_REG 0xBC 0x20 @@ -1451,7 +1453,7 @@ APB_SARADC - Successive Approximation Register Analog to Digital Converter + SAR (Successive Approximation Register) Analog-to-Digital Converter APB_SARADC 0x60040000 @@ -2348,7 +2350,7 @@ - C0RE_0_MONTR_ENA + CORE_0_MONTR_ENA ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG 0x0 0x20 @@ -3355,6 +3357,51 @@ + + BB + BB Peripheral + BB + 0x6001D000 + + 0x0 + 0x4 + registers + + + + BBPD_CTRL + Baseband control register + 0x54 + 0x20 + + + DC_EST_FORCE_PD + 0 + 1 + read-write + + + DC_EST_FORCE_PU + 1 + 1 + read-write + + + FFT_FORCE_PD + 2 + 1 + read-write + + + FFT_FORCE_PU + 3 + 1 + read-write + + + + + DMA DMA (Direct Memory Access) Controller @@ -3377,103 +3424,110 @@ DMA_CH2 46 + + DMA_APBPERI_PMS + 55 + - INT_RAW_CH0 - DMA_INT_RAW_CH0_REG. + 3 + 0x10 + 0-2 + INT_RAW_CH%s + DMA_INT_RAW_CH%s_REG. 0x0 0x20 - IN_DONE_CH0_INT_RAW + IN_DONE The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. 0 1 - read-only + read-write - IN_SUC_EOF_CH0_INT_RAW + IN_SUC_EOF The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0. 1 1 - read-only + read-write - IN_ERR_EOF_CH0_INT_RAW + IN_ERR_EOF The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved. 2 1 - read-only + read-write - OUT_DONE_CH0_INT_RAW + OUT_DONE The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0. 3 1 - read-only + read-write - OUT_EOF_CH0_INT_RAW + OUT_EOF The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0. 4 1 - read-only + read-write - IN_DSCR_ERR_CH0_INT_RAW + IN_DSCR_ERR The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0. 5 1 - read-only + read-write - OUT_DSCR_ERR_CH0_INT_RAW + OUT_DSCR_ERR The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0. 6 1 - read-only + read-write - IN_DSCR_EMPTY_CH0_INT_RAW + IN_DSCR_EMPTY The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0. 7 1 - read-only + read-write - OUT_TOTAL_EOF_CH0_INT_RAW + OUT_TOTAL_EOF The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0. 8 1 - read-only + read-write - INFIFO_OVF_CH0_INT_RAW + INFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow. 9 1 - read-only + read-write - INFIFO_UDF_CH0_INT_RAW + INFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow. 10 1 - read-only + read-write - OUTFIFO_OVF_CH0_INT_RAW + OUTFIFO_OVF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow. 11 1 - read-only + read-write - OUTFIFO_UDF_CH0_INT_RAW + OUTFIFO_UDF This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow. 12 1 - read-only + read-write @@ -3484,91 +3538,91 @@ 0x20 - IN_DONE_CH0_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH0_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH0_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH0_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH0_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH0_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH0_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH0_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH0_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH0_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH0_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH0_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH0_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3577,97 +3631,100 @@ - INT_ENA_CH0 - DMA_INT_ENA_CH0_REG. + 3 + 0x10 + 0-2 + INT_ENA_CH%s + DMA_INT_ENA_CH%s_REG. 0x8 0x20 - IN_DONE_CH0_INT_ENA + IN_DONE The interrupt enable bit for the IN_DONE_CH_INT interrupt. 0 1 read-write - IN_SUC_EOF_CH0_INT_ENA + IN_SUC_EOF The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-write - IN_ERR_EOF_CH0_INT_ENA + IN_ERR_EOF The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-write - OUT_DONE_CH0_INT_ENA + OUT_DONE The interrupt enable bit for the OUT_DONE_CH_INT interrupt. 3 1 read-write - OUT_EOF_CH0_INT_ENA + OUT_EOF The interrupt enable bit for the OUT_EOF_CH_INT interrupt. 4 1 read-write - IN_DSCR_ERR_CH0_INT_ENA + IN_DSCR_ERR The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-write - OUT_DSCR_ERR_CH0_INT_ENA + OUT_DSCR_ERR The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-write - IN_DSCR_EMPTY_CH0_INT_ENA + IN_DSCR_EMPTY The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-write - OUT_TOTAL_EOF_CH0_INT_ENA + OUT_TOTAL_EOF The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-write - INFIFO_OVF_CH0_INT_ENA + INFIFO_OVF The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-write - INFIFO_UDF_CH0_INT_ENA + INFIFO_UDF The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-write - OUTFIFO_OVF_CH0_INT_ENA + OUTFIFO_OVF The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-write - OUTFIFO_UDF_CH0_INT_ENA + OUTFIFO_UDF The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3676,97 +3733,100 @@ - INT_CLR_CH0 - DMA_INT_CLR_CH0_REG. + 3 + 0x10 + 0-2 + INT_CLR_CH%s + DMA_INT_CLR_CH%s_REG. 0xC 0x20 - IN_DONE_CH0_INT_CLR + IN_DONE Set this bit to clear the IN_DONE_CH_INT interrupt. 0 1 write-only - IN_SUC_EOF_CH0_INT_CLR + IN_SUC_EOF Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. 1 1 write-only - IN_ERR_EOF_CH0_INT_CLR + IN_ERR_EOF Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. 2 1 write-only - OUT_DONE_CH0_INT_CLR + OUT_DONE Set this bit to clear the OUT_DONE_CH_INT interrupt. 3 1 write-only - OUT_EOF_CH0_INT_CLR + OUT_EOF Set this bit to clear the OUT_EOF_CH_INT interrupt. 4 1 write-only - IN_DSCR_ERR_CH0_INT_CLR + IN_DSCR_ERR Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. 5 1 write-only - OUT_DSCR_ERR_CH0_INT_CLR + OUT_DSCR_ERR Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. 6 1 write-only - IN_DSCR_EMPTY_CH0_INT_CLR + IN_DSCR_EMPTY Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 write-only - OUT_TOTAL_EOF_CH0_INT_CLR + OUT_TOTAL_EOF Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 write-only - INFIFO_OVF_CH0_INT_CLR + INFIFO_OVF Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. 9 1 write-only - INFIFO_UDF_CH0_INT_CLR + INFIFO_UDF Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. 10 1 write-only - OUTFIFO_OVF_CH0_INT_CLR + OUTFIFO_OVF Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 write-only - OUTFIFO_UDF_CH0_INT_CLR + OUTFIFO_UDF Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3774,105 +3834,6 @@ - - INT_RAW_CH1 - DMA_INT_RAW_CH1_REG. - 0x10 - 0x20 - - - IN_DONE_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. - 0 - 1 - read-only - - - IN_SUC_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1. - 1 - 1 - read-only - - - IN_ERR_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved. - 2 - 1 - read-only - - - OUT_DONE_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1. - 3 - 1 - read-only - - - OUT_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1. - 4 - 1 - read-only - - - IN_DSCR_ERR_CH1_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1. - 5 - 1 - read-only - - - OUT_DSCR_ERR_CH1_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1. - 6 - 1 - read-only - - - IN_DSCR_EMPTY_CH1_INT_RAW - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1. - 7 - 1 - read-only - - - OUT_TOTAL_EOF_CH1_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1. - 8 - 1 - read-only - - - INFIFO_OVF_CH1_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow. - 9 - 1 - read-only - - - INFIFO_UDF_CH1_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow. - 10 - 1 - read-only - - - OUTFIFO_OVF_CH1_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow. - 11 - 1 - read-only - - - OUTFIFO_UDF_CH1_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow. - 12 - 1 - read-only - - - INT_ST_CH1 DMA_INT_ST_CH1_REG. @@ -3880,91 +3841,91 @@ 0x20 - IN_DONE_CH1_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH1_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH1_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH1_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH1_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH1_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH1_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH1_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH1_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH1_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH1_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH1_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH1_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -3972,303 +3933,6 @@ - - INT_ENA_CH1 - DMA_INT_ENA_CH1_REG. - 0x18 - 0x20 - - - IN_DONE_CH1_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH1_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH1_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_DONE_CH1_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 3 - 1 - read-write - - - OUT_EOF_CH1_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 4 - 1 - read-write - - - IN_DSCR_ERR_CH1_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 5 - 1 - read-write - - - OUT_DSCR_ERR_CH1_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 6 - 1 - read-write - - - IN_DSCR_EMPTY_CH1_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 7 - 1 - read-write - - - OUT_TOTAL_EOF_CH1_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 8 - 1 - read-write - - - INFIFO_OVF_CH1_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 9 - 1 - read-write - - - INFIFO_UDF_CH1_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 10 - 1 - read-write - - - OUTFIFO_OVF_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 11 - 1 - read-write - - - OUTFIFO_UDF_CH1_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 12 - 1 - read-write - - - - - INT_CLR_CH1 - DMA_INT_CLR_CH1_REG. - 0x1C - 0x20 - - - IN_DONE_CH1_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH1_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH1_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_DONE_CH1_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 3 - 1 - write-only - - - OUT_EOF_CH1_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 4 - 1 - write-only - - - IN_DSCR_ERR_CH1_INT_CLR - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. - 5 - 1 - write-only - - - OUT_DSCR_ERR_CH1_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 6 - 1 - write-only - - - IN_DSCR_EMPTY_CH1_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 7 - 1 - write-only - - - OUT_TOTAL_EOF_CH1_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 8 - 1 - write-only - - - INFIFO_OVF_CH1_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 9 - 1 - write-only - - - INFIFO_UDF_CH1_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 10 - 1 - write-only - - - OUTFIFO_OVF_CH1_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 11 - 1 - write-only - - - OUTFIFO_UDF_CH1_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 12 - 1 - write-only - - - - - INT_RAW_CH2 - DMA_INT_RAW_CH2_REG. - 0x20 - 0x20 - - - IN_DONE_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. - 0 - 1 - read-only - - - IN_SUC_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2. - 1 - 1 - read-only - - - IN_ERR_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved. - 2 - 1 - read-only - - - OUT_DONE_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2. - 3 - 1 - read-only - - - OUT_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2. - 4 - 1 - read-only - - - IN_DSCR_ERR_CH2_INT_RAW - The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2. - 5 - 1 - read-only - - - OUT_DSCR_ERR_CH2_INT_RAW - The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2. - 6 - 1 - read-only - - - IN_DSCR_EMPTY_CH2_INT_RAW - The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2. - 7 - 1 - read-only - - - OUT_TOTAL_EOF_CH2_INT_RAW - The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2. - 8 - 1 - read-only - - - INFIFO_OVF_CH2_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow. - 9 - 1 - read-only - - - INFIFO_UDF_CH2_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow. - 10 - 1 - read-only - - - OUTFIFO_OVF_CH2_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow. - 11 - 1 - read-only - - - OUTFIFO_UDF_CH2_INT_RAW - This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow. - 12 - 1 - read-only - - - INT_ST_CH2 DMA_INT_ST_CH2_REG. @@ -4276,91 +3940,91 @@ 0x20 - IN_DONE_CH2_INT_ST + IN_DONE The raw interrupt status bit for the IN_DONE_CH_INT interrupt. 0 1 read-only - IN_SUC_EOF_CH2_INT_ST + IN_SUC_EOF The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt. 1 1 read-only - IN_ERR_EOF_CH2_INT_ST + IN_ERR_EOF The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt. 2 1 read-only - OUT_DONE_CH2_INT_ST + OUT_DONE The raw interrupt status bit for the OUT_DONE_CH_INT interrupt. 3 1 read-only - OUT_EOF_CH2_INT_ST + OUT_EOF The raw interrupt status bit for the OUT_EOF_CH_INT interrupt. 4 1 read-only - IN_DSCR_ERR_CH2_INT_ST + IN_DSCR_ERR The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt. 5 1 read-only - OUT_DSCR_ERR_CH2_INT_ST + OUT_DSCR_ERR The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt. 6 1 read-only - IN_DSCR_EMPTY_CH2_INT_ST + IN_DSCR_EMPTY The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt. 7 1 read-only - OUT_TOTAL_EOF_CH2_INT_ST + OUT_TOTAL_EOF The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt. 8 1 read-only - INFIFO_OVF_CH2_INT_ST + INFIFO_OVF The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt. 9 1 read-only - INFIFO_UDF_CH2_INT_ST + INFIFO_UDF The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt. 10 1 read-only - OUTFIFO_OVF_CH2_INT_ST + OUTFIFO_OVF The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt. 11 1 read-only - OUTFIFO_UDF_CH2_INT_ST + OUTFIFO_UDF The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt. 12 1 @@ -4368,204 +4032,6 @@ - - INT_ENA_CH2 - DMA_INT_ENA_CH2_REG. - 0x28 - 0x20 - - - IN_DONE_CH2_INT_ENA - The interrupt enable bit for the IN_DONE_CH_INT interrupt. - 0 - 1 - read-write - - - IN_SUC_EOF_CH2_INT_ENA - The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - read-write - - - IN_ERR_EOF_CH2_INT_ENA - The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - read-write - - - OUT_DONE_CH2_INT_ENA - The interrupt enable bit for the OUT_DONE_CH_INT interrupt. - 3 - 1 - read-write - - - OUT_EOF_CH2_INT_ENA - The interrupt enable bit for the OUT_EOF_CH_INT interrupt. - 4 - 1 - read-write - - - IN_DSCR_ERR_CH2_INT_ENA - The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt. - 5 - 1 - read-write - - - OUT_DSCR_ERR_CH2_INT_ENA - The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt. - 6 - 1 - read-write - - - IN_DSCR_EMPTY_CH2_INT_ENA - The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt. - 7 - 1 - read-write - - - OUT_TOTAL_EOF_CH2_INT_ENA - The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt. - 8 - 1 - read-write - - - INFIFO_OVF_CH2_INT_ENA - The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt. - 9 - 1 - read-write - - - INFIFO_UDF_CH2_INT_ENA - The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt. - 10 - 1 - read-write - - - OUTFIFO_OVF_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt. - 11 - 1 - read-write - - - OUTFIFO_UDF_CH2_INT_ENA - The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt. - 12 - 1 - read-write - - - - - INT_CLR_CH2 - DMA_INT_CLR_CH2_REG. - 0x2C - 0x20 - - - IN_DONE_CH2_INT_CLR - Set this bit to clear the IN_DONE_CH_INT interrupt. - 0 - 1 - write-only - - - IN_SUC_EOF_CH2_INT_CLR - Set this bit to clear the IN_SUC_EOF_CH_INT interrupt. - 1 - 1 - write-only - - - IN_ERR_EOF_CH2_INT_CLR - Set this bit to clear the IN_ERR_EOF_CH_INT interrupt. - 2 - 1 - write-only - - - OUT_DONE_CH2_INT_CLR - Set this bit to clear the OUT_DONE_CH_INT interrupt. - 3 - 1 - write-only - - - OUT_EOF_CH2_INT_CLR - Set this bit to clear the OUT_EOF_CH_INT interrupt. - 4 - 1 - write-only - - - IN_DSCR_ERR_CH2_INT_CLR - Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt. - 5 - 1 - write-only - - - OUT_DSCR_ERR_CH2_INT_CLR - Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt. - 6 - 1 - write-only - - - IN_DSCR_EMPTY_CH2_INT_CLR - Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt. - 7 - 1 - write-only - - - OUT_TOTAL_EOF_CH2_INT_CLR - Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt. - 8 - 1 - write-only - - - INFIFO_OVF_CH2_INT_CLR - Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt. - 9 - 1 - write-only - - - INFIFO_UDF_CH2_INT_CLR - Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt. - 10 - 1 - write-only - - - OUTFIFO_OVF_CH2_INT_CLR - Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt. - 11 - 1 - write-only - - - OUTFIFO_UDF_CH2_INT_CLR - Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt. - 12 - 1 - write-only - - - AHB_TEST DMA_AHB_TEST_REG. @@ -4634,41 +4100,44 @@ - IN_CONF0_CH0 - DMA_IN_CONF0_CH0_REG. + 3 + 0xC0 + 0-2 + IN_CONF0_CH%s + DMA_IN_CONF%s_CH%s_REG. 0x70 0x20 - IN_RST_CH0 + IN_RST This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer. 0 1 read-write - IN_LOOP_TEST_CH0 + IN_LOOP_TEST reserved 1 1 read-write - INDSCR_BURST_EN_CH0 + INDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM. 2 1 read-write - IN_DATA_BURST_EN_CH0 + IN_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM. 3 1 read-write - MEM_TRANS_EN_CH0 + MEM_TRANS_EN Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. 4 1 @@ -4683,7 +4152,7 @@ 0x20 - IN_CHECK_OWNER_CH0 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -4699,56 +4168,56 @@ 0x07800003 - INFIFO_FULL_CH0 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 0. 0 1 read-only - INFIFO_EMPTY_CH0 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 0. 1 1 read-only - INFIFO_CNT_CH0 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0. 2 6 read-only - IN_REMAIN_UNDER_1B_CH0 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH0 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH0 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH0 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH0 + IN_BUF_HUNGRY reserved 27 1 @@ -4764,14 +4233,14 @@ 0x00000800 - INFIFO_RDATA_CH0 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH0 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -4780,49 +4249,52 @@ - IN_LINK_CH0 - DMA_IN_LINK_CH0_REG. + 3 + 0xC0 + 0-2 + IN_LINK_CH%s + DMA_IN_LINK_CH%s_REG. 0x80 0x20 0x01100000 - INLINK_ADDR_CH0 + INLINK_ADDR This register stores the 20 least significant bits of the first inlink descriptor's address. 0 20 read-write - INLINK_AUTO_RET_CH0 + INLINK_AUTO_RET Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. 20 1 read-write - INLINK_STOP_CH0 + INLINK_STOP Set this bit to stop dealing with the inlink descriptors. 21 1 read-write - INLINK_START_CH0 + INLINK_START Set this bit to start dealing with the inlink descriptors. 22 1 read-write - INLINK_RESTART_CH0 + INLINK_RESTART Set this bit to mount a new inlink descriptor. 23 1 read-write - INLINK_PARK_CH0 + INLINK_PARK 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. 24 1 @@ -4837,21 +4309,21 @@ 0x20 - INLINK_DSCR_ADDR_CH0 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH0 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH0 + IN_STATE reserved 20 3 @@ -4866,7 +4338,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH0 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -4881,7 +4353,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH0 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -4896,7 +4368,7 @@ 0x20 - INLINK_DSCR_CH0 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -4905,13 +4377,16 @@ - IN_DSCR_BF0_CH0 - DMA_IN_DSCR_BF0_CH0_REG. + 3 + 0xC0 + 0-2 + IN_DSCR_BF0_CH%s + DMA_IN_DSCR_BF%s_CH%s_REG. 0x94 0x20 - INLINK_DSCR_BF0_CH0 + INLINK_DSCR_BF0 The address of the last inlink descriptor x-1. 0 32 @@ -4926,7 +4401,7 @@ 0x20 - INLINK_DSCR_BF1_CH0 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -4935,13 +4410,16 @@ - IN_PRI_CH0 - DMA_IN_PRI_CH0_REG. + 3 + 0xC0 + 0-2 + IN_PRI_CH%s + DMA_IN_PRI_CH%s_REG. 0x9C 0x20 - RX_PRI_CH0 + RX_PRI The priority of Rx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -4950,14 +4428,17 @@ - IN_PERI_SEL_CH0 - DMA_IN_PERI_SEL_CH0_REG. + 3 + 0xC0 + 0-2 + IN_PERI_SEL_CH%s + DMA_IN_PERI_SEL_CH%s_REG. 0xA0 0x20 0x0000003F - PERI_IN_SEL_CH0 + PERI_IN_SEL This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -4966,49 +4447,52 @@ - OUT_CONF0_CH0 - DMA_OUT_CONF0_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_CONF0_CH%s + DMA_OUT_CONF%s_CH%s_REG. 0xD0 0x20 0x00000008 - OUT_RST_CH0 + OUT_RST This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer. 0 1 read-write - OUT_LOOP_TEST_CH0 + OUT_LOOP_TEST reserved 1 1 read-write - OUT_AUTO_WRBACK_CH0 + OUT_AUTO_WRBACK Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. 2 1 read-write - OUT_EOF_MODE_CH0 + OUT_EOF_MODE EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA 3 1 read-write - OUTDSCR_BURST_EN_CH0 + OUTDSCR_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM. 4 1 read-write - OUT_DATA_BURST_EN_CH0 + OUT_DATA_BURST_EN Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM. 5 1 @@ -5017,13 +4501,16 @@ - OUT_CONF1_CH0 - DMA_OUT_CONF1_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_CONF1_CH%s + DMA_OUT_CONF1_CH%s_REG. 0xD4 0x20 - OUT_CHECK_OWNER_CH0 + OUT_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -5039,49 +4526,49 @@ 0x07800002 - OUTFIFO_FULL_CH0 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 0. 0 1 read-only - OUTFIFO_EMPTY_CH0 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 0. 1 1 read-only - OUTFIFO_CNT_CH0 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH0 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH0 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH0 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH0 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -5096,14 +4583,14 @@ 0x20 - OUTFIFO_WDATA_CH0 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH0 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -5112,42 +4599,45 @@ - OUT_LINK_CH0 - DMA_OUT_LINK_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_LINK_CH%s + DMA_OUT_LINK_CH%s_REG. 0xE0 0x20 0x00800000 - OUTLINK_ADDR_CH0 + OUTLINK_ADDR This register stores the 20 least significant bits of the first outlink descriptor's address. 0 20 read-write - OUTLINK_STOP_CH0 + OUTLINK_STOP Set this bit to stop dealing with the outlink descriptors. 20 1 read-write - OUTLINK_START_CH0 + OUTLINK_START Set this bit to start dealing with the outlink descriptors. 21 1 read-write - OUTLINK_RESTART_CH0 + OUTLINK_RESTART Set this bit to restart a new outlink from the last address. 22 1 read-write - OUTLINK_PARK_CH0 + OUTLINK_PARK 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. 23 1 @@ -5162,21 +4652,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH0 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH0 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH0 + OUT_STATE reserved 20 3 @@ -5185,13 +4675,16 @@ - OUT_EOF_DES_ADDR_CH0 - DMA_OUT_EOF_DES_ADDR_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_EOF_DES_ADDR_CH%s + DMA_OUT_EOF_DES_ADDR_CH%s_REG. 0xE8 0x20 - OUT_EOF_DES_ADDR_CH0 + OUT_EOF_DES_ADDR This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5206,7 +4699,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH0 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -5221,7 +4714,7 @@ 0x20 - OUTLINK_DSCR_CH0 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -5236,7 +4729,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH0 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -5251,7 +4744,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH0 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5260,13 +4753,16 @@ - OUT_PRI_CH0 - DMA_OUT_PRI_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_PRI_CH%s + DMA_OUT_PRI_CH%s_REG. 0xFC 0x20 - TX_PRI_CH0 + TX_PRI The priority of Tx channel 0. The larger of the value, the higher of the priority. 0 4 @@ -5275,14 +4771,17 @@ - OUT_PERI_SEL_CH0 - DMA_OUT_PERI_SEL_CH0_REG. + 3 + 0xC0 + 0-2 + OUT_PERI_SEL_CH%s + DMA_OUT_PERI_SEL_CH%s_REG. 0x100 0x20 0x0000003F - PERI_OUT_SEL_CH0 + PERI_OUT_SEL This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. 0 6 @@ -5290,49 +4789,6 @@ - - IN_CONF0_CH1 - DMA_IN_CONF0_CH1_REG. - 0x130 - 0x20 - - - IN_RST_CH1 - This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer. - 0 - 1 - read-write - - - IN_LOOP_TEST_CH1 - reserved - 1 - 1 - read-write - - - INDSCR_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM. - 2 - 1 - read-write - - - IN_DATA_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM. - 3 - 1 - read-write - - - MEM_TRANS_EN_CH1 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. - 4 - 1 - read-write - - - IN_CONF1_CH1 DMA_IN_CONF1_CH1_REG. @@ -5340,7 +4796,7 @@ 0x20 - IN_CHECK_OWNER_CH1 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -5356,56 +4812,56 @@ 0x07800003 - INFIFO_FULL_CH1 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 1. 0 1 read-only - INFIFO_EMPTY_CH1 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 1. 1 1 read-only - INFIFO_CNT_CH1 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1. 2 6 read-only - IN_REMAIN_UNDER_1B_CH1 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH1 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH1 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH1 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH1 + IN_BUF_HUNGRY reserved 27 1 @@ -5421,14 +4877,14 @@ 0x00000800 - INFIFO_RDATA_CH1 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH1 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -5436,57 +4892,6 @@ - - IN_LINK_CH1 - DMA_IN_LINK_CH1_REG. - 0x140 - 0x20 - 0x01100000 - - - INLINK_ADDR_CH1 - This register stores the 20 least significant bits of the first inlink descriptor's address. - 0 - 20 - read-write - - - INLINK_AUTO_RET_CH1 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 - read-write - - - INLINK_STOP_CH1 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 - read-write - - - INLINK_START_CH1 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 - read-write - - - INLINK_RESTART_CH1 - Set this bit to mount a new inlink descriptor. - 23 - 1 - read-write - - - INLINK_PARK_CH1 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 - 1 - read-only - - - IN_STATE_CH1 DMA_IN_STATE_CH1_REG. @@ -5494,21 +4899,21 @@ 0x20 - INLINK_DSCR_ADDR_CH1 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH1 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH1 + IN_STATE reserved 20 3 @@ -5523,7 +4928,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH1 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -5538,7 +4943,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH1 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -5553,7 +4958,7 @@ 0x20 - INLINK_DSCR_CH1 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -5561,21 +4966,6 @@ - - IN_DSCR_BF0_CH1 - DMA_IN_DSCR_BF0_CH1_REG. - 0x154 - 0x20 - - - INLINK_DSCR_BF0_CH1 - The address of the last inlink descriptor x-1. - 0 - 32 - read-only - - - IN_DSCR_BF1_CH1 DMA_IN_DSCR_BF1_CH1_REG. @@ -5583,7 +4973,7 @@ 0x20 - INLINK_DSCR_BF1_CH1 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5591,103 +4981,6 @@ - - IN_PRI_CH1 - DMA_IN_PRI_CH1_REG. - 0x15C - 0x20 - - - RX_PRI_CH1 - The priority of Rx channel 1. The larger of the value, the higher of the priority. - 0 - 4 - read-write - - - - - IN_PERI_SEL_CH1 - DMA_IN_PERI_SEL_CH1_REG. - 0x160 - 0x20 - 0x0000003F - - - PERI_IN_SEL_CH1 - This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. - 0 - 6 - read-write - - - - - OUT_CONF0_CH1 - DMA_OUT_CONF0_CH1_REG. - 0x190 - 0x20 - 0x00000008 - - - OUT_RST_CH1 - This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer. - 0 - 1 - read-write - - - OUT_LOOP_TEST_CH1 - reserved - 1 - 1 - read-write - - - OUT_AUTO_WRBACK_CH1 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - 2 - 1 - read-write - - - OUT_EOF_MODE_CH1 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA - 3 - 1 - read-write - - - OUTDSCR_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM. - 4 - 1 - read-write - - - OUT_DATA_BURST_EN_CH1 - Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM. - 5 - 1 - read-write - - - - - OUT_CONF1_CH1 - DMA_OUT_CONF1_CH1_REG. - 0x194 - 0x20 - - - OUT_CHECK_OWNER_CH1 - Set this bit to enable checking the owner attribute of the link descriptor. - 12 - 1 - read-write - - - OUTFIFO_STATUS_CH1 DMA_OUTFIFO_STATUS_CH1_REG. @@ -5696,49 +4989,49 @@ 0x07800002 - OUTFIFO_FULL_CH1 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 1. 0 1 read-only - OUTFIFO_EMPTY_CH1 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 1. 1 1 read-only - OUTFIFO_CNT_CH1 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH1 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH1 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH1 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH1 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -5753,14 +5046,14 @@ 0x20 - OUTFIFO_WDATA_CH1 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH1 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -5768,50 +5061,6 @@ - - OUT_LINK_CH1 - DMA_OUT_LINK_CH1_REG. - 0x1A0 - 0x20 - 0x00800000 - - - OUTLINK_ADDR_CH1 - This register stores the 20 least significant bits of the first outlink descriptor's address. - 0 - 20 - read-write - - - OUTLINK_STOP_CH1 - Set this bit to stop dealing with the outlink descriptors. - 20 - 1 - read-write - - - OUTLINK_START_CH1 - Set this bit to start dealing with the outlink descriptors. - 21 - 1 - read-write - - - OUTLINK_RESTART_CH1 - Set this bit to restart a new outlink from the last address. - 22 - 1 - read-write - - - OUTLINK_PARK_CH1 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 23 - 1 - read-only - - - OUT_STATE_CH1 DMA_OUT_STATE_CH1_REG. @@ -5819,21 +5068,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH1 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH1 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH1 + OUT_STATE reserved 20 3 @@ -5841,21 +5090,6 @@ - - OUT_EOF_DES_ADDR_CH1 - DMA_OUT_EOF_DES_ADDR_CH1_REG. - 0x1A8 - 0x20 - - - OUT_EOF_DES_ADDR_CH1 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - OUT_EOF_BFR_DES_ADDR_CH1 DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG. @@ -5863,7 +5097,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH1 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -5878,7 +5112,7 @@ 0x20 - OUTLINK_DSCR_CH1 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -5893,7 +5127,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH1 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -5908,7 +5142,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH1 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -5916,80 +5150,6 @@ - - OUT_PRI_CH1 - DMA_OUT_PRI_CH1_REG. - 0x1BC - 0x20 - - - TX_PRI_CH1 - The priority of Tx channel 1. The larger of the value, the higher of the priority. - 0 - 4 - read-write - - - - - OUT_PERI_SEL_CH1 - DMA_OUT_PERI_SEL_CH1_REG. - 0x1C0 - 0x20 - 0x0000003F - - - PERI_OUT_SEL_CH1 - This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. - 0 - 6 - read-write - - - - - IN_CONF0_CH2 - DMA_IN_CONF0_CH2_REG. - 0x1F0 - 0x20 - - - IN_RST_CH2 - This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer. - 0 - 1 - read-write - - - IN_LOOP_TEST_CH2 - reserved - 1 - 1 - read-write - - - INDSCR_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM. - 2 - 1 - read-write - - - IN_DATA_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM. - 3 - 1 - read-write - - - MEM_TRANS_EN_CH2 - Set this bit 1 to enable automatic transmitting data from memory to memory via DMA. - 4 - 1 - read-write - - - IN_CONF1_CH2 DMA_IN_CONF1_CH2_REG. @@ -5997,7 +5157,7 @@ 0x20 - IN_CHECK_OWNER_CH2 + IN_CHECK_OWNER Set this bit to enable checking the owner attribute of the link descriptor. 12 1 @@ -6013,56 +5173,56 @@ 0x07800003 - INFIFO_FULL_CH2 + INFIFO_FULL L1 Rx FIFO full signal for Rx channel 2. 0 1 read-only - INFIFO_EMPTY_CH2 + INFIFO_EMPTY L1 Rx FIFO empty signal for Rx channel 2. 1 1 read-only - INFIFO_CNT_CH2 + INFIFO_CNT The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2. 2 6 read-only - IN_REMAIN_UNDER_1B_CH2 + IN_REMAIN_UNDER_1B reserved 23 1 read-only - IN_REMAIN_UNDER_2B_CH2 + IN_REMAIN_UNDER_2B reserved 24 1 read-only - IN_REMAIN_UNDER_3B_CH2 + IN_REMAIN_UNDER_3B reserved 25 1 read-only - IN_REMAIN_UNDER_4B_CH2 + IN_REMAIN_UNDER_4B reserved 26 1 read-only - IN_BUF_HUNGRY_CH2 + IN_BUF_HUNGRY reserved 27 1 @@ -6078,14 +5238,14 @@ 0x00000800 - INFIFO_RDATA_CH2 + INFIFO_RDATA This register stores the data popping from DMA FIFO. 0 12 read-only - INFIFO_POP_CH2 + INFIFO_POP Set this bit to pop data from DMA FIFO. 12 1 @@ -6093,57 +5253,6 @@ - - IN_LINK_CH2 - DMA_IN_LINK_CH2_REG. - 0x200 - 0x20 - 0x01100000 - - - INLINK_ADDR_CH2 - This register stores the 20 least significant bits of the first inlink descriptor's address. - 0 - 20 - read-write - - - INLINK_AUTO_RET_CH2 - Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data. - 20 - 1 - read-write - - - INLINK_STOP_CH2 - Set this bit to stop dealing with the inlink descriptors. - 21 - 1 - read-write - - - INLINK_START_CH2 - Set this bit to start dealing with the inlink descriptors. - 22 - 1 - read-write - - - INLINK_RESTART_CH2 - Set this bit to mount a new inlink descriptor. - 23 - 1 - read-write - - - INLINK_PARK_CH2 - 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working. - 24 - 1 - read-only - - - IN_STATE_CH2 DMA_IN_STATE_CH2_REG. @@ -6151,21 +5260,21 @@ 0x20 - INLINK_DSCR_ADDR_CH2 + INLINK_DSCR_ADDR This register stores the current inlink descriptor's address. 0 18 read-only - IN_DSCR_STATE_CH2 + IN_DSCR_STATE reserved 18 2 read-only - IN_STATE_CH2 + IN_STATE reserved 20 3 @@ -6180,7 +5289,7 @@ 0x20 - IN_SUC_EOF_DES_ADDR_CH2 + IN_SUC_EOF_DES_ADDR This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1. 0 32 @@ -6195,7 +5304,7 @@ 0x20 - IN_ERR_EOF_DES_ADDR_CH2 + IN_ERR_EOF_DES_ADDR This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0. 0 32 @@ -6210,7 +5319,7 @@ 0x20 - INLINK_DSCR_CH2 + INLINK_DSCR The address of the current inlink descriptor x. 0 32 @@ -6218,21 +5327,6 @@ - - IN_DSCR_BF0_CH2 - DMA_IN_DSCR_BF0_CH2_REG. - 0x214 - 0x20 - - - INLINK_DSCR_BF0_CH2 - The address of the last inlink descriptor x-1. - 0 - 32 - read-only - - - IN_DSCR_BF1_CH2 DMA_IN_DSCR_BF1_CH2_REG. @@ -6240,7 +5334,7 @@ 0x20 - INLINK_DSCR_BF1_CH2 + INLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -6248,103 +5342,6 @@ - - IN_PRI_CH2 - DMA_IN_PRI_CH2_REG. - 0x21C - 0x20 - - - RX_PRI_CH2 - The priority of Rx channel 2. The larger of the value, the higher of the priority. - 0 - 4 - read-write - - - - - IN_PERI_SEL_CH2 - DMA_IN_PERI_SEL_CH2_REG. - 0x220 - 0x20 - 0x0000003F - - - PERI_IN_SEL_CH2 - This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. - 0 - 6 - read-write - - - - - OUT_CONF0_CH2 - DMA_OUT_CONF0_CH2_REG. - 0x250 - 0x20 - 0x00000008 - - - OUT_RST_CH2 - This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer. - 0 - 1 - read-write - - - OUT_LOOP_TEST_CH2 - reserved - 1 - 1 - read-write - - - OUT_AUTO_WRBACK_CH2 - Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted. - 2 - 1 - read-write - - - OUT_EOF_MODE_CH2 - EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA - 3 - 1 - read-write - - - OUTDSCR_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM. - 4 - 1 - read-write - - - OUT_DATA_BURST_EN_CH2 - Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM. - 5 - 1 - read-write - - - - - OUT_CONF1_CH2 - DMA_OUT_CONF1_CH2_REG. - 0x254 - 0x20 - - - OUT_CHECK_OWNER_CH2 - Set this bit to enable checking the owner attribute of the link descriptor. - 12 - 1 - read-write - - - OUTFIFO_STATUS_CH2 DMA_OUTFIFO_STATUS_CH2_REG. @@ -6353,49 +5350,49 @@ 0x07800002 - OUTFIFO_FULL_CH2 + OUTFIFO_FULL L1 Tx FIFO full signal for Tx channel 2. 0 1 read-only - OUTFIFO_EMPTY_CH2 + OUTFIFO_EMPTY L1 Tx FIFO empty signal for Tx channel 2. 1 1 read-only - OUTFIFO_CNT_CH2 + OUTFIFO_CNT The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2. 2 6 read-only - OUT_REMAIN_UNDER_1B_CH2 + OUT_REMAIN_UNDER_1B reserved 23 1 read-only - OUT_REMAIN_UNDER_2B_CH2 + OUT_REMAIN_UNDER_2B reserved 24 1 read-only - OUT_REMAIN_UNDER_3B_CH2 + OUT_REMAIN_UNDER_3B reserved 25 1 read-only - OUT_REMAIN_UNDER_4B_CH2 + OUT_REMAIN_UNDER_4B reserved 26 1 @@ -6410,14 +5407,14 @@ 0x20 - OUTFIFO_WDATA_CH2 + OUTFIFO_WDATA This register stores the data that need to be pushed into DMA FIFO. 0 9 read-write - OUTFIFO_PUSH_CH2 + OUTFIFO_PUSH Set this bit to push data into DMA FIFO. 9 1 @@ -6425,50 +5422,6 @@ - - OUT_LINK_CH2 - DMA_OUT_LINK_CH2_REG. - 0x260 - 0x20 - 0x00800000 - - - OUTLINK_ADDR_CH2 - This register stores the 20 least significant bits of the first outlink descriptor's address. - 0 - 20 - read-write - - - OUTLINK_STOP_CH2 - Set this bit to stop dealing with the outlink descriptors. - 20 - 1 - read-write - - - OUTLINK_START_CH2 - Set this bit to start dealing with the outlink descriptors. - 21 - 1 - read-write - - - OUTLINK_RESTART_CH2 - Set this bit to restart a new outlink from the last address. - 22 - 1 - read-write - - - OUTLINK_PARK_CH2 - 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working. - 23 - 1 - read-only - - - OUT_STATE_CH2 DMA_OUT_STATE_CH2_REG. @@ -6476,21 +5429,21 @@ 0x20 - OUTLINK_DSCR_ADDR_CH2 + OUTLINK_DSCR_ADDR This register stores the current outlink descriptor's address. 0 18 read-only - OUT_DSCR_STATE_CH2 + OUT_DSCR_STATE reserved 18 2 read-only - OUT_STATE_CH2 + OUT_STATE reserved 20 3 @@ -6498,21 +5451,6 @@ - - OUT_EOF_DES_ADDR_CH2 - DMA_OUT_EOF_DES_ADDR_CH2_REG. - 0x268 - 0x20 - - - OUT_EOF_DES_ADDR_CH2 - This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1. - 0 - 32 - read-only - - - OUT_EOF_BFR_DES_ADDR_CH2 DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG. @@ -6520,7 +5458,7 @@ 0x20 - OUT_EOF_BFR_DES_ADDR_CH2 + OUT_EOF_BFR_DES_ADDR This register stores the address of the outlink descriptor before the last outlink descriptor. 0 32 @@ -6535,7 +5473,7 @@ 0x20 - OUTLINK_DSCR_CH2 + OUTLINK_DSCR The address of the current outlink descriptor y. 0 32 @@ -6550,7 +5488,7 @@ 0x20 - OUTLINK_DSCR_BF0_CH2 + OUTLINK_DSCR_BF0 The address of the last outlink descriptor y-1. 0 32 @@ -6565,7 +5503,7 @@ 0x20 - OUTLINK_DSCR_BF1_CH2 + OUTLINK_DSCR_BF1 The address of the second-to-last inlink descriptor x-2. 0 32 @@ -6573,37 +5511,6 @@ - - OUT_PRI_CH2 - DMA_OUT_PRI_CH2_REG. - 0x27C - 0x20 - - - TX_PRI_CH2 - The priority of Tx channel 2. The larger of the value, the higher of the priority. - 0 - 4 - read-write - - - - - OUT_PERI_SEL_CH2 - DMA_OUT_PERI_SEL_CH2_REG. - 0x280 - 0x20 - 0x0000003F - - - PERI_OUT_SEL_CH2 - This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC. - 0 - 6 - read-write - - - @@ -6613,57 +5520,57 @@ 0x6003D000 0x0 - 0xA4C + 0x108C registers - 512 - 0x1 + 128 + 0x4 Y_MEM[%s] memory that stores Y 0x0 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 M_MEM[%s] memory that stores M 0x200 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 RB_MEM[%s] memory that stores Rb 0x400 - 0x8 + 0x20 - 48 - 0x1 + 12 + 0x4 BOX_MEM[%s] memory that stores BOX 0x600 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 X_MEM[%s] memory that stores X 0x800 - 0x8 + 0x20 - 512 - 0x1 + 128 + 0x4 Z_MEM[%s] memory that stores Z 0xA00 - 0x8 + 0x20 SET_START @@ -9125,7 +8032,7 @@ CLK - eFuse clcok configuration register. + eFuse clock configuration register. 0x1C8 0x20 0x00000002 @@ -9162,7 +8069,7 @@ CONF - eFuse operation mode configuraiton register; + eFuse operation mode configuration register. 0x1CC 0x20 @@ -9411,7 +8318,7 @@ WR_TIM_CONF1 - Configurarion register 1 of eFuse programming timing parameters. + Configuration register 1 of eFuse programming timing parameters. 0x1F0 0x20 0x00288000 @@ -9427,7 +8334,7 @@ WR_TIM_CONF2 - Configurarion register 2 of eFuse programming timing parameters. + Configuration register 2 of eFuse programming timing parameters. 0x1F4 0x20 0x00000190 @@ -11190,55 +10097,56 @@ 26 0x4 + 0-25 PIN%s GPIO pin configuration register 0x74 0x20 - PIN_SYNC2_BYPASS - set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge. + SYNC2_BYPASS + set GPIO input_sync2 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 0 2 read-write - PIN_PAD_DRIVER - set this bit to select pad driver. 1:open-drain. :normal. + PAD_DRIVER + set this bit to select pad driver. 1:open-drain. 0:normal. 2 1 read-write - PIN_SYNC1_BYPASS - set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge. + SYNC1_BYPASS + set GPIO input_sync1 signal mode. 0:disable. 1:trigger at negedge. 2or3:trigger at posedge. 3 2 read-write - PIN_INT_TYPE - set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level + INT_TYPE + set this value to choose interrupt mode. 0:disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level 7 3 read-write - PIN_WAKEUP_ENABLE + WAKEUP_ENABLE set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode) 10 1 read-write - PIN_CONFIG + CONFIG reserved 11 2 read-write - PIN_INT_ENA + INT_ENA set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt. 13 5 @@ -11264,6 +10172,7 @@ 128 0x4 + 0-127 FUNC%s_IN_SEL_CFG GPIO input function configuration register 0x154 @@ -11271,21 +10180,21 @@ IN_SEL - set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level. + set this value: s=0-53: connect GPIO[s] to this port. s=0x38: set this port always high level. s=0x3C: set this port always low level. 0 5 read-write IN_INV_SEL - set this bit to invert input signal. 1:invert. :not invert. + set this bit to invert input signal. 1:invert. 0:not invert. 5 1 read-write SEL - set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO. + set this bit to bypass GPIO. 1:do not bypass GPIO. 0:bypass GPIO. 6 1 read-write @@ -11295,6 +10204,7 @@ 26 0x4 + 0-25 FUNC%s_OUT_SEL_CFG GPIO output function select register 0x554 @@ -11303,28 +10213,28 @@ OUT_SEL - The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. + The value of the bits: 0<=s<=256. Set the value to select output signal. s=0-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n]. 0 8 read-write INV_SEL - set this bit to invert output signal.1:invert.:not invert. + set this bit to invert output signal.1:invert.0:not invert. 8 1 read-write OEN_SEL - set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal. + set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.0:use peripheral output enable signal. 9 1 read-write OEN_INV_SEL - set this bit to invert output enable signal.1:invert.:not invert. + set this bit to invert output enable signal.1:invert.0:not invert. 10 1 read-write @@ -11366,7 +10276,7 @@ - GPIOSD + GPIO_SD Sigma-Delta Modulation GPIOSD 0x60004F00 @@ -11463,7 +10373,7 @@ 0x6003E000 0x0 - 0xA0 + 0xA4 registers @@ -11624,7 +10534,7 @@ 0x20 - QUREY_CHECK + QUERY_CHECK Hmac configuration state. 0: key are agree with purpose. 1: error 0 1 @@ -11648,20 +10558,20 @@ - 64 - 0x1 + 16 + 0x4 WR_MESSAGE_MEM[%s] Message block memory. 0x80 - 0x8 + 0x20 - 32 - 0x1 + 8 + 0x4 RD_RESULT_MEM[%s] Result from upstream. 0xC0 - 0x8 + 0x20 SET_MESSAGE_PAD @@ -11727,7 +10637,7 @@ I2C0 - I2C (Inter-Integrated Circuit) Controller + I2C (Inter-Integrated Circuit) Controller 0 I2C 0x60013000 @@ -11735,6 +10645,10 @@ 0x90 registers + + I2C_MASTER + 11 + I2C_EXT0 29 @@ -12846,6 +11760,7 @@ 8 0x4 + 0-7 COMD%s I2C_COMD%s_REG 0x58 @@ -13027,8 +11942,8 @@ - I2S - I2S (Inter-IC Sound) Controller + I2S0 + I2S (Inter-IC Sound) Controller 0 I2S 0x6002D000 @@ -13037,7 +11952,7 @@ registers - I2S + I2S0 20 @@ -14302,7 +13217,7 @@ INTERRUPT_CORE0 - Interrupt Core + Interrupt Controller (Core 0) INTERRUPT_CORE0 0x600C2000 @@ -14310,6 +13225,110 @@ 0x19C registers + + WIFI_MAC + 0 + + + WIFI_MAC_NMI + 1 + + + WIFI_PWR + 2 + + + WIFI_BB + 3 + + + BT_MAC + 4 + + + BT_BB + 5 + + + BT_BB_NMI + 6 + + + RWBT + 7 + + + RWBLE + 8 + + + RWBT_NMI + 9 + + + RWBLE_NMI + 10 + + + SLC0 + 12 + + + SLC1 + 13 + + + CACHE_IA + 36 + + + ICACHE_PRELOAD0 + 41 + + + ICACHE_SYNC0 + 42 + + + FROM_CPU_INTR0 + 50 + + + FROM_CPU_INTR1 + 51 + + + FROM_CPU_INTR2 + 52 + + + FROM_CPU_INTR3 + 53 + + + CORE0_IRAM0_PMS + 56 + + + CORE0_DRAM0_PMS + 57 + + + CORE0_PIF_PMS + 58 + + + CORE0_PIF_PMS_SIZE + 59 + + + BAK_PMS_VIOLATE + 60 + + + CACHE_CORE0_ACS + 61 + MAC_INTR_MAP @@ -16021,57 +15040,68 @@ LEDC 23 + + TIMER1 + 30 + + + TIMER2 + 31 + - LSCH0_CONF0 - LEDC_LSCH0_CONF0. + 6 + 0x14 + 0-5 + CH%s_CONF0 + LEDC_LSCH%s_CONF%s. 0x0 0x20 - TIMER_SEL_LSCH0 + TIMER_SEL reg_timer_sel_lsch0. 0 2 read-write - SIG_OUT_EN_LSCH0 + SIG_OUT_EN reg_sig_out_en_lsch0. 2 1 read-write - IDLE_LV_LSCH0 + IDLE_LV reg_idle_lv_lsch0. 3 1 read-write - PARA_UP_LSCH0 + PARA_UP reg_para_up_lsch0. 4 1 write-only - OVF_NUM_LSCH0 + OVF_NUM reg_ovf_num_lsch0. 5 10 read-write - OVF_CNT_EN_LSCH0 + OVF_CNT_EN reg_ovf_cnt_en_lsch0. 15 1 read-write - OVF_CNT_RESET_LSCH0 + OVF_CNT_RESET reg_ovf_cnt_reset_lsch0. 16 1 @@ -16080,13 +15110,16 @@ - LSCH0_HPOINT - LEDC_LSCH0_HPOINT. + 6 + 0x14 + 0-5 + CH%s_HPOINT + LEDC_LSCH%s_HPOINT. 0x4 0x20 - HPOINT_LSCH0 + HPOINT reg_hpoint_lsch0. 0 14 @@ -16095,13 +15128,16 @@ - LSCH0_DUTY - LEDC_LSCH0_DUTY. + 6 + 0x14 + 0-5 + CH%s_DUTY + LEDC_LSCH%s_DUTY. 0x8 0x20 - DUTY_LSCH0 + DUTY reg_duty_lsch0. 0 19 @@ -16110,42 +15146,45 @@ - LSCH0_CONF1 - LEDC_LSCH0_CONF1. + 6 + 0x14 + 0-5 + CH%s_CONF1 + LEDC_LSCH%s_CONF1. 0xC 0x20 0x40000000 - DUTY_SCALE_LSCH0 + DUTY_SCALE reg_duty_scale_lsch0. 0 10 read-write - DUTY_CYCLE_LSCH0 + DUTY_CYCLE reg_duty_cycle_lsch0. 10 10 read-write - DUTY_NUM_LSCH0 + DUTY_NUM reg_duty_num_lsch0. 20 10 read-write - DUTY_INC_LSCH0 + DUTY_INC reg_duty_inc_lsch0. 30 1 read-write - DUTY_START_LSCH0 + DUTY_START reg_duty_start_lsch0. 31 1 @@ -16154,13 +15193,16 @@ - LSCH0_DUTY_R - LEDC_LSCH0_DUTY_R. + 6 + 0x14 + 0-5 + CH%s_DUTY_R + LEDC_LSCH%s_DUTY_R. 0x10 0x20 - DUTY_LSCH0_R + DUTY_R reg_duty_lsch0_r. 0 19 @@ -16169,779 +15211,52 @@ - LSCH1_CONF0 - LEDC_LSCH1_CONF0. - 0x14 - 0x20 - - - TIMER_SEL_LSCH1 - reg_timer_sel_lsch1. - 0 - 2 - read-write - - - SIG_OUT_EN_LSCH1 - reg_sig_out_en_lsch1. - 2 - 1 - read-write - - - IDLE_LV_LSCH1 - reg_idle_lv_lsch1. - 3 - 1 - read-write - - - PARA_UP_LSCH1 - reg_para_up_lsch1. - 4 - 1 - write-only - - - OVF_NUM_LSCH1 - reg_ovf_num_lsch1. - 5 - 10 - read-write - - - OVF_CNT_EN_LSCH1 - reg_ovf_cnt_en_lsch1. - 15 - 1 - read-write - - - OVF_CNT_RESET_LSCH1 - reg_ovf_cnt_reset_lsch1. - 16 - 1 - write-only - - - - - LSCH1_HPOINT - LEDC_LSCH1_HPOINT. - 0x18 - 0x20 - - - HPOINT_LSCH1 - reg_hpoint_lsch1. - 0 - 14 - read-write - - - - - LSCH1_DUTY - LEDC_LSCH1_DUTY. - 0x1C - 0x20 - - - DUTY_LSCH1 - reg_duty_lsch1. - 0 - 19 - read-write - - - - - LSCH1_CONF1 - LEDC_LSCH1_CONF1. - 0x20 - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH1 - reg_duty_scale_lsch1. - 0 - 10 - read-write - - - DUTY_CYCLE_LSCH1 - reg_duty_cycle_lsch1. - 10 - 10 - read-write - - - DUTY_NUM_LSCH1 - reg_duty_num_lsch1. - 20 - 10 - read-write - - - DUTY_INC_LSCH1 - reg_duty_inc_lsch1. - 30 - 1 - read-write - - - DUTY_START_LSCH1 - reg_duty_start_lsch1. - 31 - 1 - read-write - - - - - LSCH1_DUTY_R - LEDC_LSCH1_DUTY_R. - 0x24 - 0x20 - - - DUTY_LSCH1_R - reg_duty_lsch1_r. - 0 - 19 - read-only - - - - - LSCH2_CONF0 - LEDC_LSCH2_CONF0. - 0x28 - 0x20 - - - TIMER_SEL_LSCH2 - reg_timer_sel_lsch2. - 0 - 2 - read-write - - - SIG_OUT_EN_LSCH2 - reg_sig_out_en_lsch2. - 2 - 1 - read-write - - - IDLE_LV_LSCH2 - reg_idle_lv_lsch2. - 3 - 1 - read-write - - - PARA_UP_LSCH2 - reg_para_up_lsch2. - 4 - 1 - write-only - - - OVF_NUM_LSCH2 - reg_ovf_num_lsch2. - 5 - 10 - read-write - - - OVF_CNT_EN_LSCH2 - reg_ovf_cnt_en_lsch2. - 15 - 1 - read-write - - - OVF_CNT_RESET_LSCH2 - reg_ovf_cnt_reset_lsch2. - 16 - 1 - write-only - - - - - LSCH2_HPOINT - LEDC_LSCH2_HPOINT. - 0x2C - 0x20 - - - HPOINT_LSCH2 - reg_hpoint_lsch2. - 0 - 14 - read-write - - - - - LSCH2_DUTY - LEDC_LSCH2_DUTY. - 0x30 - 0x20 - - - DUTY_LSCH2 - reg_duty_lsch2. - 0 - 19 - read-write - - - - - LSCH2_CONF1 - LEDC_LSCH2_CONF1. - 0x34 - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH2 - reg_duty_scale_lsch2. - 0 - 10 - read-write - - - DUTY_CYCLE_LSCH2 - reg_duty_cycle_lsch2. - 10 - 10 - read-write - - - DUTY_NUM_LSCH2 - reg_duty_num_lsch2. - 20 - 10 - read-write - - - DUTY_INC_LSCH2 - reg_duty_inc_lsch2. - 30 - 1 - read-write - - - DUTY_START_LSCH2 - reg_duty_start_lsch2. - 31 - 1 - read-write - - - - - LSCH2_DUTY_R - LEDC_LSCH2_DUTY_R. - 0x38 - 0x20 - - - DUTY_LSCH2_R - reg_duty_lsch2_r. - 0 - 19 - read-only - - - - - LSCH3_CONF0 - LEDC_LSCH3_CONF0. - 0x3C - 0x20 - - - TIMER_SEL_LSCH3 - reg_timer_sel_lsch3. - 0 - 2 - read-write - - - SIG_OUT_EN_LSCH3 - reg_sig_out_en_lsch3. - 2 - 1 - read-write - - - IDLE_LV_LSCH3 - reg_idle_lv_lsch3. - 3 - 1 - read-write - - - PARA_UP_LSCH3 - reg_para_up_lsch3. - 4 - 1 - write-only - - - OVF_NUM_LSCH3 - reg_ovf_num_lsch3. - 5 - 10 - read-write - - - OVF_CNT_EN_LSCH3 - reg_ovf_cnt_en_lsch3. - 15 - 1 - read-write - - - OVF_CNT_RESET_LSCH3 - reg_ovf_cnt_reset_lsch3. - 16 - 1 - write-only - - - - - LSCH3_HPOINT - LEDC_LSCH3_HPOINT. - 0x40 - 0x20 - - - HPOINT_LSCH3 - reg_hpoint_lsch3. - 0 - 14 - read-write - - - - - LSCH3_DUTY - LEDC_LSCH3_DUTY. - 0x44 - 0x20 - - - DUTY_LSCH3 - reg_duty_lsch3. - 0 - 19 - read-write - - - - - LSCH3_CONF1 - LEDC_LSCH3_CONF1. - 0x48 - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH3 - reg_duty_scale_lsch3. - 0 - 10 - read-write - - - DUTY_CYCLE_LSCH3 - reg_duty_cycle_lsch3. - 10 - 10 - read-write - - - DUTY_NUM_LSCH3 - reg_duty_num_lsch3. - 20 - 10 - read-write - - - DUTY_INC_LSCH3 - reg_duty_inc_lsch3. - 30 - 1 - read-write - - - DUTY_START_LSCH3 - reg_duty_start_lsch3. - 31 - 1 - read-write - - - - - LSCH3_DUTY_R - LEDC_LSCH3_DUTY_R. - 0x4C - 0x20 - - - DUTY_LSCH3_R - reg_duty_lsch3_r. - 0 - 19 - read-only - - - - - LSCH4_CONF0 - LEDC_LSCH4_CONF0. - 0x50 - 0x20 - - - TIMER_SEL_LSCH4 - reg_timer_sel_lsch4. - 0 - 2 - read-write - - - SIG_OUT_EN_LSCH4 - reg_sig_out_en_lsch4. - 2 - 1 - read-write - - - IDLE_LV_LSCH4 - reg_idle_lv_lsch4. - 3 - 1 - read-write - - - PARA_UP_LSCH4 - reg_para_up_lsch4. - 4 - 1 - write-only - - - OVF_NUM_LSCH4 - reg_ovf_num_lsch4. - 5 - 10 - read-write - - - OVF_CNT_EN_LSCH4 - reg_ovf_cnt_en_lsch4. - 15 - 1 - read-write - - - OVF_CNT_RESET_LSCH4 - reg_ovf_cnt_reset_lsch4. - 16 - 1 - write-only - - - - - LSCH4_HPOINT - LEDC_LSCH4_HPOINT. - 0x54 - 0x20 - - - HPOINT_LSCH4 - reg_hpoint_lsch4. - 0 - 14 - read-write - - - - - LSCH4_DUTY - LEDC_LSCH4_DUTY. - 0x58 - 0x20 - - - DUTY_LSCH4 - reg_duty_lsch4. - 0 - 19 - read-write - - - - - LSCH4_CONF1 - LEDC_LSCH4_CONF1. - 0x5C - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH4 - reg_duty_scale_lsch4. - 0 - 10 - read-write - - - DUTY_CYCLE_LSCH4 - reg_duty_cycle_lsch4. - 10 - 10 - read-write - - - DUTY_NUM_LSCH4 - reg_duty_num_lsch4. - 20 - 10 - read-write - - - DUTY_INC_LSCH4 - reg_duty_inc_lsch4. - 30 - 1 - read-write - - - DUTY_START_LSCH4 - reg_duty_start_lsch4. - 31 - 1 - read-write - - - - - LSCH4_DUTY_R - LEDC_LSCH4_DUTY_R. - 0x60 - 0x20 - - - DUTY_LSCH4_R - reg_duty_lsch4_r. - 0 - 19 - read-only - - - - - LSCH5_CONF0 - LEDC_LSCH5_CONF0. - 0x64 - 0x20 - - - TIMER_SEL_LSCH5 - reg_timer_sel_lsch5. - 0 - 2 - read-write - - - SIG_OUT_EN_LSCH5 - reg_sig_out_en_lsch5. - 2 - 1 - read-write - - - IDLE_LV_LSCH5 - reg_idle_lv_lsch5. - 3 - 1 - read-write - - - PARA_UP_LSCH5 - reg_para_up_lsch5. - 4 - 1 - write-only - - - OVF_NUM_LSCH5 - reg_ovf_num_lsch5. - 5 - 10 - read-write - - - OVF_CNT_EN_LSCH5 - reg_ovf_cnt_en_lsch5. - 15 - 1 - read-write - - - OVF_CNT_RESET_LSCH5 - reg_ovf_cnt_reset_lsch5. - 16 - 1 - write-only - - - - - LSCH5_HPOINT - LEDC_LSCH5_HPOINT. - 0x68 - 0x20 - - - HPOINT_LSCH5 - reg_hpoint_lsch5. - 0 - 14 - read-write - - - - - LSCH5_DUTY - LEDC_LSCH5_DUTY. - 0x6C - 0x20 - - - DUTY_LSCH5 - reg_duty_lsch5. - 0 - 19 - read-write - - - - - LSCH5_CONF1 - LEDC_LSCH5_CONF1. - 0x70 - 0x20 - 0x40000000 - - - DUTY_SCALE_LSCH5 - reg_duty_scale_lsch5. - 0 - 10 - read-write - - - DUTY_CYCLE_LSCH5 - reg_duty_cycle_lsch5. - 10 - 10 - read-write - - - DUTY_NUM_LSCH5 - reg_duty_num_lsch5. - 20 - 10 - read-write - - - DUTY_INC_LSCH5 - reg_duty_inc_lsch5. - 30 - 1 - read-write - - - DUTY_START_LSCH5 - reg_duty_start_lsch5. - 31 - 1 - read-write - - - - - LSCH5_DUTY_R - LEDC_LSCH5_DUTY_R. - 0x74 - 0x20 - - - DUTY_LSCH5_R - reg_duty_lsch5_r. - 0 - 19 - read-only - - - - - LSTIMER0_CONF - LEDC_LSTIMER0_CONF. + 4 + 0x8 + 0-3 + TIMER%s_CONF + LEDC_LSTIMER%s_CONF. 0xA0 0x20 0x00800000 - LSTIMER0_DUTY_RES + DUTY_RES reg_lstimer0_duty_res. 0 4 read-write - CLK_DIV_LSTIMER0 + CLK_DIV reg_clk_div_lstimer0. 4 18 read-write - LSTIMER0_PAUSE + PAUSE reg_lstimer0_pause. 22 1 read-write - LSTIMER0_RST + RST reg_lstimer0_rst. 23 1 read-write - TICK_SEL_LSTIMER0 + TICK_SEL reg_tick_sel_lstimer0. 24 1 read-write - LSTIMER0_PARA_UP + PARA_UP reg_lstimer0_para_up. 25 1 @@ -16950,13 +15265,16 @@ - LSTIMER0_VALUE - LEDC_LSTIMER0_VALUE. + 4 + 0x8 + 0-3 + TIMER%s_VALUE + LEDC_LSTIMER%s_VALUE. 0xA4 0x20 - LSTIMER0_CNT + CNT reg_lstimer0_cnt. 0 14 @@ -16964,204 +15282,6 @@ - - LSTIMER1_CONF - LEDC_LSTIMER1_CONF. - 0xA8 - 0x20 - 0x00800000 - - - LSTIMER1_DUTY_RES - reg_lstimer1_duty_res. - 0 - 4 - read-write - - - CLK_DIV_LSTIMER1 - reg_clk_div_lstimer1. - 4 - 18 - read-write - - - LSTIMER1_PAUSE - reg_lstimer1_pause. - 22 - 1 - read-write - - - LSTIMER1_RST - reg_lstimer1_rst. - 23 - 1 - read-write - - - TICK_SEL_LSTIMER1 - reg_tick_sel_lstimer1. - 24 - 1 - read-write - - - LSTIMER1_PARA_UP - reg_lstimer1_para_up. - 25 - 1 - write-only - - - - - LSTIMER1_VALUE - LEDC_LSTIMER1_VALUE. - 0xAC - 0x20 - - - LSTIMER1_CNT - reg_lstimer1_cnt. - 0 - 14 - read-only - - - - - LSTIMER2_CONF - LEDC_LSTIMER2_CONF. - 0xB0 - 0x20 - 0x00800000 - - - LSTIMER2_DUTY_RES - reg_lstimer2_duty_res. - 0 - 4 - read-write - - - CLK_DIV_LSTIMER2 - reg_clk_div_lstimer2. - 4 - 18 - read-write - - - LSTIMER2_PAUSE - reg_lstimer2_pause. - 22 - 1 - read-write - - - LSTIMER2_RST - reg_lstimer2_rst. - 23 - 1 - read-write - - - TICK_SEL_LSTIMER2 - reg_tick_sel_lstimer2. - 24 - 1 - read-write - - - LSTIMER2_PARA_UP - reg_lstimer2_para_up. - 25 - 1 - write-only - - - - - LSTIMER2_VALUE - LEDC_LSTIMER2_VALUE. - 0xB4 - 0x20 - - - LSTIMER2_CNT - reg_lstimer2_cnt. - 0 - 14 - read-only - - - - - LSTIMER3_CONF - LEDC_LSTIMER3_CONF. - 0xB8 - 0x20 - 0x00800000 - - - LSTIMER3_DUTY_RES - reg_lstimer3_duty_res. - 0 - 4 - read-write - - - CLK_DIV_LSTIMER3 - reg_clk_div_lstimer3. - 4 - 18 - read-write - - - LSTIMER3_PAUSE - reg_lstimer3_pause. - 22 - 1 - read-write - - - LSTIMER3_RST - reg_lstimer3_rst. - 23 - 1 - read-write - - - TICK_SEL_LSTIMER3 - reg_tick_sel_lstimer3. - 24 - 1 - read-write - - - LSTIMER3_PARA_UP - reg_lstimer3_para_up. - 25 - 1 - write-only - - - - - LSTIMER3_VALUE - LEDC_LSTIMER3_VALUE. - 0xBC - 0x20 - - - LSTIMER3_CNT - reg_lstimer3_cnt. - 0 - 14 - read-only - - - INT_RAW LEDC_INT_RAW. @@ -17173,112 +15293,112 @@ reg_lstimer0_ovf_int_raw. 0 1 - read-only + read-write LSTIMER1_OVF_INT_RAW reg_lstimer1_ovf_int_raw. 1 1 - read-only + read-write LSTIMER2_OVF_INT_RAW reg_lstimer2_ovf_int_raw. 2 1 - read-only + read-write LSTIMER3_OVF_INT_RAW reg_lstimer3_ovf_int_raw. 3 1 - read-only + read-write DUTY_CHNG_END_LSCH0_INT_RAW reg_duty_chng_end_lsch0_int_raw. 4 1 - read-only + read-write DUTY_CHNG_END_LSCH1_INT_RAW reg_duty_chng_end_lsch1_int_raw. 5 1 - read-only + read-write DUTY_CHNG_END_LSCH2_INT_RAW reg_duty_chng_end_lsch2_int_raw. 6 1 - read-only + read-write DUTY_CHNG_END_LSCH3_INT_RAW reg_duty_chng_end_lsch3_int_raw. 7 1 - read-only + read-write DUTY_CHNG_END_LSCH4_INT_RAW reg_duty_chng_end_lsch4_int_raw. 8 1 - read-only + read-write DUTY_CHNG_END_LSCH5_INT_RAW reg_duty_chng_end_lsch5_int_raw. 9 1 - read-only + read-write OVF_CNT_LSCH0_INT_RAW reg_ovf_cnt_lsch0_int_raw. 10 1 - read-only + read-write OVF_CNT_LSCH1_INT_RAW reg_ovf_cnt_lsch1_int_raw. 11 1 - read-only + read-write OVF_CNT_LSCH2_INT_RAW reg_ovf_cnt_lsch2_int_raw. 12 1 - read-only + read-write OVF_CNT_LSCH3_INT_RAW reg_ovf_cnt_lsch3_int_raw. 13 1 - read-only + read-write OVF_CNT_LSCH4_INT_RAW reg_ovf_cnt_lsch4_int_raw. 14 1 - read-only + read-write OVF_CNT_LSCH5_INT_RAW reg_ovf_cnt_lsch5_int_raw. 15 1 - read-only + read-write @@ -17684,7 +15804,7 @@ RMT - Remote Control Peripheral + Remote Control RMT 0x60016000 @@ -17698,8 +15818,11 @@ - CH0DATA - RMT_CH0DATA_REG. + 4 + 0x4 + 0-3 + CH%sDATA + RMT_CH%sDATA_REG. 0x0 0x20 @@ -17712,51 +15835,6 @@ - - CH1DATA - RMT_CH1DATA_REG. - 0x4 - 0x20 - - - DATA - Reserved. - 0 - 32 - read-write - - - - - CH2DATA - RMT_CH2DATA_REG. - 0x8 - 0x20 - - - DATA - Reserved. - 0 - 32 - read-write - - - - - CH3DATA - RMT_CH3DATA_REG. - 0xC - 0x20 - - - DATA - Reserved. - 0 - 32 - read-write - - - 2 0x4 @@ -17922,7 +16000,10 @@ - CH2CONF1 + 2 + 0x8 + 2-3 + CH%s_RX_CONF1 RMT_CH2CONF1_REG. 0x1C 0x20 @@ -17994,80 +16075,11 @@ - CH3CONF1 - RMT_CH3CONF1_REG. - 0x24 - 0x20 - 0x000001E8 - - - RX_EN - reg_rx_en_ch3. - 0 - 1 - read-write - - - MEM_WR_RST - reg_mem_wr_rst_ch3. - 1 - 1 - write-only - - - APB_MEM_RST - reg_apb_mem_rst_ch3. - 2 - 1 - write-only - - - MEM_OWNER - reg_mem_owner_ch3. - 3 - 1 - read-write - - - RX_FILTER_EN - reg_rx_filter_en_ch3. - 4 - 1 - read-write - - - RX_FILTER_THRES - reg_rx_filter_thres_ch3. - 5 - 8 - read-write - - - MEM_RX_WRAP_EN - reg_mem_rx_wrap_en_ch3. - 13 - 1 - read-write - - - AFIFO_RST - reg_afifo_rst_ch3. - 14 - 1 - write-only - - - CONF_UPDATE - reg_conf_update_ch3. - 15 - 1 - write-only - - - - - CH0STATUS - RMT_CH0STATUS_REG. + 2 + 0x4 + 0-1 + CH%s_TX_STATUS + RMT_CH%sSTATUS_REG. 0x28 0x20 @@ -18123,64 +16135,10 @@ - CH1STATUS - RMT_CH1STATUS_REG. - 0x2C - 0x20 - - - MEM_RADDR_EX - reg_mem_raddr_ex_ch1. - 0 - 9 - read-only - - - STATE - reg_state_ch1. - 9 - 3 - read-only - - - APB_MEM_WADDR - reg_apb_mem_waddr_ch1. - 12 - 9 - read-only - - - APB_MEM_RD_ERR - reg_apb_mem_rd_err_ch1. - 21 - 1 - read-only - - - MEM_EMPTY - reg_mem_empty_ch1. - 22 - 1 - read-only - - - APB_MEM_WR_ERR - reg_apb_mem_wr_err_ch1. - 23 - 1 - read-only - - - APB_MEM_RADDR - reg_apb_mem_raddr_ch1. - 24 - 8 - read-only - - - - - CH2STATUS + 2 + 0x4 + 2-3 + CH%s_RX_STATUS RMT_CH2STATUS_REG. 0x30 0x20 @@ -18229,56 +16187,6 @@ - - CH3STATUS - RMT_CH3STATUS_REG. - 0x34 - 0x20 - - - MEM_WADDR_EX - reg_mem_waddr_ex_ch3. - 0 - 9 - read-only - - - APB_MEM_RADDR - reg_apb_mem_raddr_ch3. - 12 - 9 - read-only - - - STATE - reg_state_ch3. - 22 - 3 - read-only - - - MEM_OWNER_ERR - reg_mem_owner_err_ch3. - 25 - 1 - read-only - - - MEM_FULL - reg_mem_full_ch3. - 26 - 1 - read-only - - - APB_MEM_RD_ERR - reg_apb_mem_rd_err_ch3. - 27 - 1 - read-only - - - INT_RAW RMT_INT_RAW_REG. @@ -18289,75 +16197,71 @@ 2 0x1 0-1 - CH%s_TX_END_INT_RAW + CH%s_TX_END reg_ch%s_tx_end_int_raw. 0 1 - read-only + read-write 2 0x1 2-3 - CH%s_RX_END_INT_RAW + CH%s_RX_END reg_ch2_rx_end_int_raw. 2 1 - read-only + read-write 2 0x1 0-1 - CH%s_TX_ERR_INT_RAW + CH%s_TX_ERR reg_ch%s_err_int_raw. 4 1 - read-only + read-write 2 0x1 2-3 - CH%s_RX_ERR_INT_RAW + CH%s_RX_ERR reg_ch2_err_int_raw. 6 1 - read-only + read-write 2 0x1 0-1 - CH%s_TX_THR_EVENT_INT_RAW + CH%s_TX_THR_EVENT reg_ch%s_tx_thr_event_int_raw. 8 1 - read-only + read-write - CH2_RX_THR_EVENT_INT_RAW + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT reg_ch2_rx_thr_event_int_raw. 10 1 - read-only - - - CH3_RX_THR_EVENT_INT_RAW - reg_ch3_rx_thr_event_int_raw. - 11 - 1 - read-only + read-write 2 0x1 0-1 - CH%s_TX_LOOP_INT_RAW + CH%s_TX_LOOP reg_ch%s_tx_loop_int_raw. 12 1 - read-only + read-write @@ -18371,7 +16275,7 @@ 2 0x1 0-1 - CH%s_TX_END_INT_ST + CH%s_TX_END reg_ch%s_tx_end_int_st. 0 1 @@ -18381,7 +16285,7 @@ 2 0x1 2-3 - CH%s_RX_END_INT_ST + CH%s_RX_END reg_ch2_rx_end_int_st. 2 1 @@ -18391,7 +16295,7 @@ 2 0x1 0-1 - CH%s_TX_ERR_INT_ST + CH%s_TX_ERR reg_ch%s_err_int_st. 4 1 @@ -18401,7 +16305,7 @@ 2 0x1 2-3 - CH%s_RX_ERR_INT_ST + CH%s_RX_ERR reg_ch2_err_int_st. 6 1 @@ -18411,31 +16315,27 @@ 2 0x1 0-1 - CH%s_TX_THR_EVENT_INT_ST + CH%s_TX_THR_EVENT reg_ch%s_tx_thr_event_int_st. 8 1 read-only - CH2_RX_THR_EVENT_INT_ST + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT reg_ch2_rx_thr_event_int_st. 10 1 read-only - - CH3_RX_THR_EVENT_INT_ST - reg_ch3_rx_thr_event_int_st. - 11 - 1 - read-only - 2 0x1 0-1 - CH%s_TX_LOOP_INT_ST + CH%s_TX_LOOP reg_ch%s_tx_loop_int_st. 12 1 @@ -18453,7 +16353,7 @@ 2 0x1 0-1 - CH%s_TX_END_INT_ENA + CH%s_TX_END reg_ch%s_tx_end_int_ena. 0 1 @@ -18463,7 +16363,7 @@ 2 0x1 2-3 - CH%s_RX_END_INT_ENA + CH%s_RX_END reg_ch2_rx_end_int_ena. 2 1 @@ -18473,7 +16373,7 @@ 2 0x1 0-1 - CH%s_TX_ERR_INT_ENA + CH%s_TX_ERR reg_ch%s_err_int_ena. 4 1 @@ -18483,7 +16383,7 @@ 2 0x1 2-3 - CH%s_RX_ERR_INT_ENA + CH%s_RX_ERR reg_ch2_err_int_ena. 6 1 @@ -18493,31 +16393,27 @@ 2 0x1 0-1 - CH%s_TX_THR_EVENT_INT_ENA + CH%s_TX_THR_EVENT reg_ch%s_tx_thr_event_int_ena. 8 1 read-write - CH2_RX_THR_EVENT_INT_ENA + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT reg_ch2_rx_thr_event_int_ena. 10 1 read-write - - CH3_RX_THR_EVENT_INT_ENA - reg_ch3_rx_thr_event_int_ena. - 11 - 1 - read-write - 2 0x1 0-1 - CH%s_TX_LOOP_INT_ENA + CH%s_TX_LOOP reg_ch%s_tx_loop_int_ena. 12 1 @@ -18535,7 +16431,7 @@ 2 0x1 0-1 - CH%s_TX_END_INT_CLR + CH%s_TX_END reg_ch%s_tx_end_int_clr. 0 1 @@ -18545,7 +16441,7 @@ 2 0x1 2-3 - CH%s_RX_END_INT_CLR + CH%s_RX_END reg_ch2_rx_end_int_clr. 2 1 @@ -18555,7 +16451,7 @@ 2 0x1 0-1 - CH%s_TX_ERR_INT_CLR + CH%s_TX_ERR reg_ch%s_err_int_clr. 4 1 @@ -18565,7 +16461,7 @@ 2 0x1 2-3 - CH%s_RX_ERR_INT_CLR + CH%s_RX_ERR reg_ch2_err_int_clr. 6 1 @@ -18575,31 +16471,27 @@ 2 0x1 0-1 - CH%s_TX_THR_EVENT_INT_CLR + CH%s_TX_THR_EVENT reg_ch%s_tx_thr_event_int_clr. 8 1 write-only - CH2_RX_THR_EVENT_INT_CLR + 2 + 0x1 + 2-3 + CH%s_RX_THR_EVENT reg_ch2_rx_thr_event_int_clr. 10 1 write-only - - CH3_RX_THR_EVENT_INT_CLR - reg_ch3_rx_thr_event_int_clr. - 11 - 1 - write-only - 2 0x1 0-1 - CH%s_TX_LOOP_INT_CLR + CH%s_TX_LOOP reg_ch%s_tx_loop_int_clr. 12 1 @@ -18608,8 +16500,11 @@ - CH0CARRIER_DUTY - RMT_CH0CARRIER_DUTY_REG. + 2 + 0x4 + 0-1 + CH%sCARRIER_DUTY + RMT_CH%sCARRIER_DUTY_REG. 0x48 0x20 0x00400040 @@ -18631,30 +16526,10 @@ - CH1CARRIER_DUTY - RMT_CH1CARRIER_DUTY_REG. - 0x4C - 0x20 - 0x00400040 - - - CARRIER_LOW - reg_carrier_low_ch1. - 0 - 16 - read-write - - - CARRIER_HIGH - reg_carrier_high_ch1. - 16 - 16 - read-write - - - - - CH2_RX_CARRIER_RM + 2 + 0x4 + 2-3 + CH%s_RX_CARRIER_RM RMT_CH2_RX_CARRIER_RM_REG. 0x50 0x20 @@ -18675,28 +16550,6 @@ - - CH3_RX_CARRIER_RM - RMT_CH3_RX_CARRIER_RM_REG. - 0x54 - 0x20 - - - CARRIER_LOW_THRES - reg_carrier_low_thres_ch3. - 0 - 16 - read-write - - - CARRIER_HIGH_THRES - reg_carrier_high_thres_ch3. - 16 - 16 - read-write - - - 2 0x4 @@ -18920,7 +16773,7 @@ RNG - Hardware random number generator + Hardware Random Number Generator RNG 0x60026000 @@ -18934,6 +16787,7 @@ Random number data 0xB0 0x20 + read-only @@ -18953,36 +16807,40 @@ - 16 - 0x1 + 96 + 0x4 M_MEM[%s] The memory that stores M 0x0 - 0x8 + 0x20 + read-write - 16 - 0x1 + 96 + 0x4 Z_MEM[%s] The memory that stores Z 0x200 - 0x8 + 0x20 + read-write - 16 - 0x1 + 96 + 0x4 Y_MEM[%s] The memory that stores Y 0x400 - 0x8 + 0x20 + read-write - 16 - 0x1 + 96 + 0x4 X_MEM[%s] The memory that stores X 0x600 - 0x8 + 0x20 + read-write M_PRIME @@ -19397,7 +17255,7 @@ read-write - RTC_MAIN_TIMER_ALARM_EN + MAIN_TIMER_ALARM_EN timer alarm enable bit 16 1 @@ -19433,7 +17291,7 @@ read-write - RTC_TIME_UPDATE + TIME_UPDATE Set 1: to update register with RTC timer 31 1 @@ -19448,7 +17306,7 @@ 0x20 - RTC_TIMER_VALUE0_LOW + TIMER_VALUE0_LOW RTC timer low 32 bits 0 32 @@ -19463,7 +17321,7 @@ 0x20 - RTC_TIMER_VALUE0_HIGH + TIMER_VALUE0_HIGH RTC timer high 16 bits 0 16 @@ -19478,14 +17336,14 @@ 0x20 - RTC_SW_CPU_INT + SW_CPU_INT rtc software interrupt to main cpu 0 1 write-only - RTC_SLP_REJECT_CAUSE_CLR + SLP_REJECT_CAUSE_CLR clear rtc sleep reject cause 1 1 @@ -19900,14 +17758,14 @@ write-only - RTC_DRESET_MASK_APPCPU + DRESET_MASK_APPCPU configure dreset configure 24 1 read-write - RTC_DRESET_MASK_PROCPU + DRESET_MASK_PROCPU configure dreset configure 25 1 @@ -19923,7 +17781,7 @@ 0x00060000 - RTC_WAKEUP_ENA + WAKEUP_ENA wakeup enable bitmap 15 17 @@ -19952,49 +17810,49 @@ read-write - RTC_WDT_INT_ENA + WDT_INT_ENA enable RTC WDT interrupt 3 1 read-write - RTC_BROWN_OUT_INT_ENA + BROWN_OUT_INT_ENA enable brown out interrupt 9 1 read-write - RTC_MAIN_TIMER_INT_ENA + MAIN_TIMER_INT_ENA enable RTC main timer interrupt 10 1 read-write - RTC_SWD_INT_ENA + SWD_INT_ENA enable super watch dog interrupt 15 1 read-write - RTC_XTAL32K_DEAD_INT_ENA + XTAL32K_DEAD_INT_ENA enable xtal32k_dead interrupt 16 1 read-write - RTC_GLITCH_DET_INT_ENA + GLITCH_DET_INT_ENA enbale gitch det interrupt 19 1 read-write - RTC_BBPLL_CAL_INT_ENA + BBPLL_CAL_INT_ENA enbale bbpll cal end interrupt 20 1 @@ -20023,49 +17881,49 @@ read-only - RTC_WDT_INT_RAW + WDT_INT_RAW RTC WDT interrupt raw 3 1 read-only - RTC_BROWN_OUT_INT_RAW + BROWN_OUT_INT_RAW brown out interrupt raw 9 1 read-only - RTC_MAIN_TIMER_INT_RAW + MAIN_TIMER_INT_RAW RTC main timer interrupt raw 10 1 read-only - RTC_SWD_INT_RAW + SWD_INT_RAW super watch dog interrupt raw 15 1 read-only - RTC_XTAL32K_DEAD_INT_RAW + XTAL32K_DEAD_INT_RAW xtal32k dead detection interrupt raw 16 1 read-only - RTC_GLITCH_DET_INT_RAW + GLITCH_DET_INT_RAW glitch_det_interrupt_raw 19 1 read-only - RTC_BBPLL_CAL_INT_RAW + BBPLL_CAL_INT_RAW bbpll cal end interrupt state 20 1 @@ -20094,49 +17952,49 @@ read-only - RTC_WDT_INT_ST + WDT_INT_ST RTC WDT interrupt state 3 1 read-only - RTC_BROWN_OUT_INT_ST + BROWN_OUT_INT_ST brown out interrupt state 9 1 read-only - RTC_MAIN_TIMER_INT_ST + MAIN_TIMER_INT_ST RTC main timer interrupt state 10 1 read-only - RTC_SWD_INT_ST + SWD_INT_ST super watch dog interrupt state 15 1 read-only - RTC_XTAL32K_DEAD_INT_ST + XTAL32K_DEAD_INT_ST xtal32k dead detection interrupt state 16 1 read-only - RTC_GLITCH_DET_INT_ST + GLITCH_DET_INT_ST glitch_det_interrupt state 19 1 read-only - RTC_BBPLL_CAL_INT_ST + BBPLL_CAL_INT_ST bbpll cal end interrupt state 20 1 @@ -20165,49 +18023,49 @@ write-only - RTC_WDT_INT_CLR + WDT_INT_CLR Clear RTC WDT interrupt state 3 1 write-only - RTC_BROWN_OUT_INT_CLR + BROWN_OUT_INT_CLR Clear brown out interrupt state 9 1 write-only - RTC_MAIN_TIMER_INT_CLR + MAIN_TIMER_INT_CLR Clear RTC main timer interrupt state 10 1 write-only - RTC_SWD_INT_CLR + SWD_INT_CLR Clear super watch dog interrupt state 15 1 write-only - RTC_XTAL32K_DEAD_INT_CLR + XTAL32K_DEAD_INT_CLR Clear RTC WDT interrupt state 16 1 write-only - RTC_GLITCH_DET_INT_CLR + GLITCH_DET_INT_CLR Clear glitch det interrupt state 19 1 write-only - RTC_BBPLL_CAL_INT_CLR + BBPLL_CAL_INT_CLR clear bbpll cal end interrupt state 20 1 @@ -20222,7 +18080,7 @@ 0x20 - RTC_SCRATCH0 + SCRATCH0 reserved register 0 32 @@ -20237,7 +18095,7 @@ 0x20 - RTC_SCRATCH1 + SCRATCH1 reserved register 0 32 @@ -20252,7 +18110,7 @@ 0x20 - RTC_SCRATCH2 + SCRATCH2 reserved register 0 32 @@ -20267,7 +18125,7 @@ 0x20 - RTC_SCRATCH3 + SCRATCH3 reserved register 0 32 @@ -20381,14 +18239,14 @@ read-write - RTC_WDT_STATE + WDT_STATE state of 32k_wdt 20 3 read-only - RTC_XTAL32K_GPIO_SEL + XTAL32K_GPIO_SEL XTAL_32K sel. 0: external XTAL_32K 23 1 @@ -20432,7 +18290,7 @@ 0x20 - RTC_SLEEP_REJECT_ENA + SLEEP_REJECT_ENA sleep reject enable 12 18 @@ -20461,14 +18319,14 @@ 0x20 - RTC_CPUSEL_CONF + CPUSEL_CONF CPU sel option 29 1 read-write - RTC_CPUPERIOD_SEL + CPUPERIOD_SEL CPU clk sel option 30 2 @@ -20626,21 +18484,21 @@ 0x00400000 - RTC_ANA_CLK_DIV_VLD + ANA_CLK_DIV_VLD used to sync div bus. clear vld before set reg_rtc_ana_clk_div 22 1 read-write - RTC_ANA_CLK_DIV + ANA_CLK_DIV the clk divider num of RTC_CLK 23 8 read-write - RTC_SLOW_CLK_NEXT_EDGE + SLOW_CLK_NEXT_EDGE flag rtc_slow_clk_next_edge 31 1 @@ -20917,7 +18775,7 @@ 0x20 - RTC_PAD_FORCE_HOLD + PAD_FORCE_HOLD rtc pad force hold 21 1 @@ -20989,14 +18847,14 @@ read-write - RTC_FASTMEM_FORCE_LPD + FASTMEM_FORCE_LPD fastmemory retention mode in sleep 15 1 read-write - RTC_FASTMEM_FORCE_LPU + FASTMEM_FORCE_LPU fastmemory donlt entry retention mode in sleep 16 1 @@ -21394,7 +19252,7 @@ 0x20 - RTC_WDT_FEED + WDT_FEED sw feed rtc wdt 31 1 @@ -21526,7 +19384,7 @@ 0x20 - RTC_SCRATCH4 + SCRATCH4 reserved register 0 32 @@ -21541,7 +19399,7 @@ 0x20 - RTC_SCRATCH5 + SCRATCH5 reserved register 0 32 @@ -21556,7 +19414,7 @@ 0x20 - RTC_SCRATCH6 + SCRATCH6 reserved register 0 32 @@ -21571,7 +19429,7 @@ 0x20 - RTC_SCRATCH7 + SCRATCH7 reserved register 0 32 @@ -21600,7 +19458,7 @@ read-only - RTC_PERI_ISO + PERI_ISO rtc peripheral iso 3 1 @@ -21642,140 +19500,140 @@ read-only - RTC_TOUCH_STATE_START + TOUCH_STATE_START touch should start to work 9 1 read-only - RTC_TOUCH_STATE_SWITCH + TOUCH_STATE_SWITCH touch is about to working. Switch rtc main state 10 1 read-only - RTC_TOUCH_STATE_SLP + TOUCH_STATE_SLP touch is in sleep state 11 1 read-only - RTC_TOUCH_STATE_DONE + TOUCH_STATE_DONE touch is done 12 1 read-only - RTC_COCPU_STATE_START + COCPU_STATE_START ulp/cocpu should start to work 13 1 read-only - RTC_COCPU_STATE_SWITCH + COCPU_STATE_SWITCH ulp/cocpu is about to working. Switch rtc main state 14 1 read-only - RTC_COCPU_STATE_SLP + COCPU_STATE_SLP ulp/cocpu is in sleep state 15 1 read-only - RTC_COCPU_STATE_DONE + COCPU_STATE_DONE ulp/cocpu is done 16 1 read-only - RTC_MAIN_STATE_XTAL_ISO + MAIN_STATE_XTAL_ISO no use any more 17 1 read-only - RTC_MAIN_STATE_PLL_ON + MAIN_STATE_PLL_ON rtc main state machine is in states that pll should be running 18 1 read-only - RTC_RDY_FOR_WAKEUP + RDY_FOR_WAKEUP rtc is ready to receive wake up trigger from wake up source 19 1 read-only - RTC_MAIN_STATE_WAIT_END + MAIN_STATE_WAIT_END rtc main state machine has been waited for some cycles 20 1 read-only - RTC_IN_WAKEUP_STATE + IN_WAKEUP_STATE rtc main state machine is in the states of wakeup process 21 1 read-only - RTC_IN_LOW_POWER_STATE + IN_LOW_POWER_STATE rtc main state machine is in the states of low power 22 1 read-only - RTC_MAIN_STATE_IN_WAIT_8M + MAIN_STATE_IN_WAIT_8M rtc main state machine is in wait 8m state 23 1 read-only - RTC_MAIN_STATE_IN_WAIT_PLL + MAIN_STATE_IN_WAIT_PLL rtc main state machine is in wait pll state 24 1 read-only - RTC_MAIN_STATE_IN_WAIT_XTL + MAIN_STATE_IN_WAIT_XTL rtc main state machine is in wait xtal state 25 1 read-only - RTC_MAIN_STATE_IN_SLP + MAIN_STATE_IN_SLP rtc main state machine is in sleep state 26 1 read-only - RTC_MAIN_STATE_IN_IDLE + MAIN_STATE_IN_IDLE rtc main state machine is in idle state 27 1 read-only - RTC_MAIN_STATE + MAIN_STATE rtc main state machine status 28 4 @@ -21790,7 +19648,7 @@ 0x20 - RTC_LOW_POWER_DIAG1 + LOW_POWER_DIAG1 0 32 read-only @@ -21804,42 +19662,42 @@ 0x20 - RTC_GPIO_PIN0_HOLD + GPIO_PIN0_HOLD the hold configure of rtc gpio0 0 1 read-write - RTC_GPIO_PIN1_HOLD + GPIO_PIN1_HOLD the hold configure of rtc gpio1 1 1 read-write - RTC_GPIO_PIN2_HOLD + GPIO_PIN2_HOLD the hold configure of rtc gpio2 2 1 read-write - RTC_GPIO_PIN3_HOLD + GPIO_PIN3_HOLD the hold configure of rtc gpio3 3 1 read-write - RTC_GPIO_PIN4_HOLD + GPIO_PIN4_HOLD the hold configure of rtc gpio4 4 1 read-write - RTC_GPIO_PIN5_HOLD + GPIO_PIN5_HOLD the hold configure of rtc gpio5 5 1 @@ -21870,63 +19728,63 @@ 0x43FF0010 - INT_WAIT + BROWN_OUT_INT_WAIT brown out interrupt wait cycles 4 10 read-write - CLOSE_FLASH_ENA + BROWN_OUT_CLOSE_FLASH_ENA enable close flash when brown out happens 14 1 read-write - PD_RF_ENA + BROWN_OUT_PD_RF_ENA enable power down RF when brown out happens 15 1 read-write - RST_WAIT + BROWN_OUT_RST_WAIT brown out reset wait cycles 16 10 read-write - RST_ENA + BROWN_OUT_RST_ENA enable brown out reset 26 1 read-write - RST_SEL + BROWN_OUT_RST_SEL 1: 4-pos reset 27 1 read-write - ANA_RST_EN + BROWN_OUT_ANA_RST_EN brown_out origin reset enable 28 1 read-write - CNT_CLR + BROWN_OUT_CNT_CLR clear brown out counter 29 1 write-only - ENA + BROWN_OUT_ENA enable brown out 30 1 @@ -21948,7 +19806,7 @@ 0x20 - RTC_TIMER_VALUE1_LOW + TIMER_VALUE1_LOW RTC timer low 32 bits 0 32 @@ -21963,7 +19821,7 @@ 0x20 - RTC_TIMER_VALUE1_HIGH + TIMER_VALUE1_HIGH RTC timer high 16 bits 0 16 @@ -22120,49 +19978,49 @@ write-only - RTC_WDT_INT_ENA_W1TS + WDT_INT_ENA_W1TS enable RTC WDT interrupt 3 1 write-only - RTC_BROWN_OUT_INT_ENA_W1TS + BROWN_OUT_INT_ENA_W1TS enable brown out interrupt 9 1 write-only - RTC_MAIN_TIMER_INT_ENA_W1TS + MAIN_TIMER_INT_ENA_W1TS enable RTC main timer interrupt 10 1 write-only - RTC_SWD_INT_ENA_W1TS + SWD_INT_ENA_W1TS enable super watch dog interrupt 15 1 write-only - RTC_XTAL32K_DEAD_INT_ENA_W1TS + XTAL32K_DEAD_INT_ENA_W1TS enable xtal32k_dead interrupt 16 1 write-only - RTC_GLITCH_DET_INT_ENA_W1TS + GLITCH_DET_INT_ENA_W1TS enbale gitch det interrupt 19 1 write-only - RTC_BBPLL_CAL_INT_ENA_W1TS + BBPLL_CAL_INT_ENA_W1TS enbale bbpll cal interrupt 20 1 @@ -22191,49 +20049,49 @@ write-only - RTC_WDT_INT_ENA_W1TC + WDT_INT_ENA_W1TC clear RTC WDT interrupt enable 3 1 write-only - RTC_BROWN_OUT_INT_ENA_W1TC + BROWN_OUT_INT_ENA_W1TC clear brown out interrupt enable 9 1 write-only - RTC_MAIN_TIMER_INT_ENA_W1TC + MAIN_TIMER_INT_ENA_W1TC Clear RTC main timer interrupt enable 10 1 write-only - RTC_SWD_INT_ENA_W1TC + SWD_INT_ENA_W1TC clear super watch dog interrupt enable 15 1 write-only - RTC_XTAL32K_DEAD_INT_ENA_W1TC + XTAL32K_DEAD_INT_ENA_W1TC clear xtal32k_dead interrupt enable 16 1 write-only - RTC_GLITCH_DET_INT_ENA_W1TC + GLITCH_DET_INT_ENA_W1TC clear gitch det interrupt enable 19 1 write-only - RTC_BBPLL_CAL_INT_ENA_W1TC + BBPLL_CAL_INT_ENA_W1TC clear bbpll cal interrupt enable 20 1 @@ -22293,7 +20151,7 @@ 0x00000007 - RTC_FIB_SEL + FIB_SEL select use analog fib signal 0 3 @@ -22308,105 +20166,105 @@ 0x20 - RTC_GPIO_WAKEUP_STATUS + GPIO_WAKEUP_STATUS rtc gpio wakeup flag 0 6 read-only - RTC_GPIO_WAKEUP_STATUS_CLR + GPIO_WAKEUP_STATUS_CLR clear rtc gpio wakeup flag 6 1 read-write - RTC_GPIO_PIN_CLK_GATE + GPIO_PIN_CLK_GATE enable rtc io clk gate 7 1 read-write - RTC_GPIO_PIN5_INT_TYPE + GPIO_PIN5_INT_TYPE configure gpio wakeup type 8 3 read-write - RTC_GPIO_PIN4_INT_TYPE + GPIO_PIN4_INT_TYPE configure gpio wakeup type 11 3 read-write - RTC_GPIO_PIN3_INT_TYPE + GPIO_PIN3_INT_TYPE configure gpio wakeup type 14 3 read-write - RTC_GPIO_PIN2_INT_TYPE + GPIO_PIN2_INT_TYPE configure gpio wakeup type 17 3 read-write - RTC_GPIO_PIN1_INT_TYPE + GPIO_PIN1_INT_TYPE configure gpio wakeup type 20 3 read-write - RTC_GPIO_PIN0_INT_TYPE + GPIO_PIN0_INT_TYPE configure gpio wakeup type 23 3 read-write - RTC_GPIO_PIN5_WAKEUP_ENABLE + GPIO_PIN5_WAKEUP_ENABLE enable wakeup from rtc gpio5 26 1 read-write - RTC_GPIO_PIN4_WAKEUP_ENABLE + GPIO_PIN4_WAKEUP_ENABLE enable wakeup from rtc gpio4 27 1 read-write - RTC_GPIO_PIN3_WAKEUP_ENABLE + GPIO_PIN3_WAKEUP_ENABLE enable wakeup from rtc gpio3 28 1 read-write - RTC_GPIO_PIN2_WAKEUP_ENABLE + GPIO_PIN2_WAKEUP_ENABLE enable wakeup from rtc gpio2 29 1 read-write - RTC_GPIO_PIN1_WAKEUP_ENABLE + GPIO_PIN1_WAKEUP_ENABLE enable wakeup from rtc gpio1 30 1 read-write - RTC_GPIO_PIN0_WAKEUP_ENABLE + GPIO_PIN0_WAKEUP_ENABLE enable wakeup from rtc gpio0 31 1 @@ -22421,49 +20279,49 @@ 0x20 - RTC_DEBUG_12M_NO_GATING + DEBUG_12M_NO_GATING use for debug 1 1 read-write - RTC_DEBUG_BIT_SEL + DEBUG_BIT_SEL use for debug 2 5 read-write - RTC_DEBUG_SEL0 + DEBUG_SEL0 use for debug 7 5 read-write - RTC_DEBUG_SEL1 + DEBUG_SEL1 use for debug 12 5 read-write - RTC_DEBUG_SEL2 + DEBUG_SEL2 use for debug 17 5 read-write - RTC_DEBUG_SEL3 + DEBUG_SEL3 use for debug 22 5 read-write - RTC_DEBUG_SEL4 + DEBUG_SEL4 use for debug 27 5 @@ -22478,84 +20336,84 @@ 0x20 - RTC_GPIO_PIN5_MUX_SEL + GPIO_PIN5_MUX_SEL use for debug 2 1 read-write - RTC_GPIO_PIN4_MUX_SEL + GPIO_PIN4_MUX_SEL use for debug 3 1 read-write - RTC_GPIO_PIN3_MUX_SEL + GPIO_PIN3_MUX_SEL use for debug 4 1 read-write - RTC_GPIO_PIN2_MUX_SEL + GPIO_PIN2_MUX_SEL use for debug 5 1 read-write - RTC_GPIO_PIN1_MUX_SEL + GPIO_PIN1_MUX_SEL use for debug 6 1 read-write - RTC_GPIO_PIN0_MUX_SEL + GPIO_PIN0_MUX_SEL use for debug 7 1 read-write - RTC_GPIO_PIN5_FUN_SEL + GPIO_PIN5_FUN_SEL use for debug 8 4 read-write - RTC_GPIO_PIN4_FUN_SEL + GPIO_PIN4_FUN_SEL use for debug 12 4 read-write - RTC_GPIO_PIN3_FUN_SEL + GPIO_PIN3_FUN_SEL use for debug 16 4 read-write - RTC_GPIO_PIN2_FUN_SEL + GPIO_PIN2_FUN_SEL use for debug 20 4 read-write - RTC_GPIO_PIN1_FUN_SEL + GPIO_PIN1_FUN_SEL use for debug 24 4 read-write - RTC_GPIO_PIN0_FUN_SEL + GPIO_PIN0_FUN_SEL use for debug 28 4 @@ -22651,7 +20509,7 @@ 0x02007270 - RTC_CNTL_DATE + DATE verision 0 28 @@ -22663,7 +20521,7 @@ SENSITIVE - Sensitive + SENSITIVE Peripheral SENSITIVE 0x600C1000 @@ -25870,7 +23728,7 @@ CLOCK_GATE - SENSITIVE_CLOCK_GATE_REG + SENSITIVE_CLOCK_GATE_REG_REG 0x170 0x20 0x00000001 @@ -25988,7 +23846,7 @@ Reserved. 1 31 - read-only + write-only @@ -26003,7 +23861,7 @@ Reserved. 1 31 - read-only + write-only @@ -26099,26 +23957,26 @@ - 64 - 0x1 + 8 + 0x4 H_MEM[%s] Sha H memory which contains intermediate hash or finial hash. 0x40 - 0x8 + 0x20 - 64 - 0x1 + 16 + 0x4 M_MEM[%s] Sha M memory which contains message. 0x80 - 0x8 + 0x20 SPI0 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 0 SPI0 0x60003000 @@ -26126,6 +23984,10 @@ 0x48 registers + + SPI_MEM_REJECT_CACHE + 40 + CTRL @@ -26753,7 +24615,7 @@ SPI1 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 1 SPI1 0x60002000 @@ -26761,6 +24623,10 @@ 0xA8 registers + + SPI1 + 18 + CMD @@ -27970,35 +25836,35 @@ The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others. 0 1 - read-only + read-write PES_END_INT_RAW The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others. 1 1 - read-only + read-write WPE_END_INT_RAW The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others. 2 1 - read-only + read-write SLV_ST_END_INT_RAW The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others 3 1 - read-only + read-write MST_ST_END_INT_RAW The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others. 4 1 - read-only + read-write @@ -28081,7 +25947,7 @@ SPI2 - SPI (Serial Peripheral Interface) Controller + SPI (Serial Peripheral Interface) Controller 2 SPI2 0x60024000 @@ -29816,7 +27682,7 @@ SYSTEM - System + System Configuration Registers SYSTEM 0x600C0000 @@ -30064,7 +27930,7 @@ read-write - CAN_CLK_EN + TWAI_CLK_EN reg_can_clk_en 19 1 @@ -30375,7 +28241,7 @@ read-write - CAN_RST + TWAI_RST reg_can_rst 19 1 @@ -30712,7 +28578,7 @@ EDMA_CTRL - edma clcok and reset register + EDMA clock and reset register 0x3C 0x20 0x00000001 @@ -31830,21 +29696,21 @@ interupt0 raw 0 1 - read-only + read-write TARGET1_INT_RAW interupt1 raw 1 1 - read-only + read-write TARGET2_INT_RAW interupt2 raw 2 1 - read-only + read-write @@ -31926,7 +29792,7 @@ TIMG0 - Timer Group + Timer Group 0 TIMG 0x6001F000 @@ -31951,49 +29817,49 @@ 0x60002000 - T0_USE_XTAL + USE_XTAL reg_t0_use_xtal. 9 1 read-write - T0_ALARM_EN + ALARM_EN reg_t0_alarm_en. 10 1 read-write - T0_DIVCNT_RST + DIVCNT_RST reg_t0_divcnt_rst. 12 1 write-only - T0_DIVIDER + DIVIDER reg_t0_divider. 13 16 read-write - T0_AUTORELOAD + AUTORELOAD reg_t0_autoreload. 29 1 read-write - T0_INCREASE + INCREASE reg_t0_increase. 30 1 read-write - T0_EN + EN reg_t0_en. 31 1 @@ -32008,7 +29874,7 @@ 0x20 - T0_LO + LO t0_lo 0 32 @@ -32023,7 +29889,7 @@ 0x20 - T0_HI + HI t0_hi 0 22 @@ -32038,7 +29904,7 @@ 0x20 - T0_UPDATE + UPDATE t0_update 31 1 @@ -32053,7 +29919,7 @@ 0x20 - T0_ALARM_LO + ALARM_LO reg_t0_alarm_lo. 0 32 @@ -32068,7 +29934,7 @@ 0x20 - T0_ALARM_HI + ALARM_HI reg_t0_alarm_hi. 0 22 @@ -32083,7 +29949,7 @@ 0x20 - T0_LOAD_LO + LOAD_LO reg_t0_load_lo. 0 32 @@ -32098,7 +29964,7 @@ 0x20 - T0_LOAD_HI + LOAD_HI reg_t0_load_hi. 0 22 @@ -32113,7 +29979,7 @@ 0x20 - T0_LOAD + LOAD t0_load 0 32 @@ -32566,7 +30432,7 @@ TIMG1 - Timer Group + Timer Group 1 0x60020000 TG1_T0_LEVEL @@ -32578,7 +30444,7 @@ - TWAI + TWAI0 Two-Wire Automotive Interface TWAI 0x6002B000 @@ -32588,7 +30454,7 @@ registers - TWAI + TWAI0 25 @@ -32867,13 +30733,15 @@ BAUD_PRESC Baud Rate Prescaler, determines the frequency dividing ratio. 0 - 13 + 14 + read-write SYNC_JUMP_WIDTH Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide. 14 2 + read-write @@ -32888,18 +30756,21 @@ The width of PBS1. 0 4 + read-write TIME_SEG2 The width of PBS2. 4 3 + read-write TIME_SAMP The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times 7 1 + read-write @@ -32959,6 +30830,7 @@ Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid). 0 8 + read-write @@ -32973,6 +30845,7 @@ The RX error counter register, reflects value changes under reception status. 0 8 + read-write @@ -32987,6 +30860,7 @@ The TX error counter register, reflects value changes under transmission status. 0 8 + read-write @@ -32998,10 +30872,10 @@ TX_BYTE_0 - In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33013,10 +30887,10 @@ TX_BYTE_1 - In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33028,10 +30902,10 @@ TX_BYTE_2 - In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33043,10 +30917,10 @@ TX_BYTE_3 - In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33058,10 +30932,10 @@ TX_BYTE_4 - In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 4 with R/W Permission. In operation mode, it stores the 4th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33073,10 +30947,10 @@ TX_BYTE_5 - In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 5 with R/W Permission. In operation mode, it stores the 5th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33088,10 +30962,10 @@ TX_BYTE_6 - In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 6 with R/W Permission. In operation mode, it stores the 6th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33103,10 +30977,10 @@ TX_BYTE_7 - In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode. + In reset mode, it is acceptance code register 7 with R/W Permission. In operation mode, it stores the 7th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33118,10 +30992,10 @@ TX_BYTE_8 - Stored the 8th byte information of the data to be transmitted under operating mode. + In operation mode, it stores the 8th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33133,10 +31007,10 @@ TX_BYTE_9 - Stored the 9th byte information of the data to be transmitted under operating mode. + In operation mode, it stores the 9th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33148,10 +31022,10 @@ TX_BYTE_10 - Stored the 10th byte information of the data to be transmitted under operating mode. + In operation mode, it stores the 10th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33163,10 +31037,10 @@ TX_BYTE_11 - Stored the 11th byte information of the data to be transmitted under operating mode. + In operation mode, it stores the 11th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33178,10 +31052,10 @@ TX_BYTE_12 - Stored the 12th byte information of the data to be transmitted under operating mode. + In operation mode, it stores the 12th byte of the data to be transmitted or received. In operation mode, writing writes to the transmit buffer while reading reads from the receive buffer. 0 8 - write-only + read-write @@ -33218,6 +31092,7 @@ This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin 8 1 + read-write @@ -33225,7 +31100,7 @@ UART0 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 0 UART 0x60000000 @@ -33265,140 +31140,140 @@ This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies. 0 1 - read-only + read-write TXFIFO_EMPTY_INT_RAW This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies . 1 1 - read-only + read-write PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error in the data. 2 1 - read-only + read-write FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error . 3 1 - read-only + read-write RXFIFO_OVF_INT_RAW This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store. 4 1 - read-only + read-write DSR_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal. 5 1 - read-only + read-write CTS_CHG_INT_RAW This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal. 6 1 - read-only + read-write BRK_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit. 7 1 - read-only + read-write RXFIFO_TOUT_INT_RAW This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte. 8 1 - read-only + read-write SW_XON_INT_RAW This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1. 9 1 - read-only + read-write SW_XOFF_INT_RAW This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1. 10 1 - read-only + read-write GLITCH_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit. 11 1 - read-only + read-write TX_BRK_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent. 12 1 - read-only + read-write TX_BRK_IDLE_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data. 13 1 - read-only + read-write TX_DONE_INT_RAW This interrupt raw bit turns to high level when transmitter has send out all data in FIFO. 14 1 - read-only + read-write RS485_PARITY_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode. 15 1 - read-only + read-write RS485_FRM_ERR_INT_RAW This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode. 16 1 - read-only + read-write RS485_CLASH_INT_RAW This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode. 17 1 - read-only + read-write AT_CMD_CHAR_DET_INT_RAW This interrupt raw bit turns to high level when receiver detects the configured at_cmd char. 18 1 - read-only + read-write WAKEUP_INT_RAW This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode. 19 1 - read-only + read-write @@ -34811,7 +32686,7 @@ UART1 - UART (Universal Asynchronous Receiver-Transmitter) Controller + UART (Universal Asynchronous Receiver-Transmitter) Controller 1 0x60010000 UART1 @@ -34820,7 +32695,7 @@ UHCI0 - Universal Host Controller Interface + Universal Host Controller Interface 0 UHCI 0x60014000 @@ -34937,49 +32812,49 @@ a 0 1 - read-only + read-write TX_START_INT_RAW a 1 1 - read-only + read-write RX_HUNG_INT_RAW a 2 1 - read-only + read-write TX_HUNG_INT_RAW a 3 1 - read-only + read-write SEND_S_REG_Q_INT_RAW a 4 1 - read-only + read-write SEND_A_REG_Q_INT_RAW a 5 1 - read-only + read-write OUT_EOF_INT_RAW This is the interrupt raw bit. Triggered when there are some errors in EOF in the 6 1 - read-only + read-write APP_CTRL0_INT_RAW @@ -35868,7 +33743,7 @@ UHCI1 - Universal Host Controller Interface + Universal Host Controller Interface 1 0x6000C000 @@ -35882,7 +33757,7 @@ registers - USB_SERIAL_JTAG + USB_DEVICE 26 @@ -35943,84 +33818,84 @@ The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG. 0 1 - read-only + read-write SOF_INT_RAW The raw interrupt bit turns to high level when SOF frame is received. 1 1 - read-only + read-write SERIAL_OUT_RECV_PKT_INT_RAW The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet. 2 1 - read-only + read-write SERIAL_IN_EMPTY_INT_RAW The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty. 3 1 - read-only + read-write PID_ERR_INT_RAW The raw interrupt bit turns to high level when pid error is detected. 4 1 - read-only + read-write CRC5_ERR_INT_RAW The raw interrupt bit turns to high level when CRC5 error is detected. 5 1 - read-only + read-write CRC16_ERR_INT_RAW The raw interrupt bit turns to high level when CRC16 error is detected. 6 1 - read-only + read-write STUFF_ERR_INT_RAW The raw interrupt bit turns to high level when stuff error is detected. 7 1 - read-only + read-write IN_TOKEN_REC_IN_EP1_INT_RAW The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received. 8 1 - read-only + read-write USB_BUS_RESET_INT_RAW The raw interrupt bit turns to high level when usb bus reset is detected. 9 1 - read-only + read-write OUT_EP1_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload. 10 1 - read-only + read-write OUT_EP2_ZERO_PAYLOAD_INT_RAW The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload. 11 1 - read-only + read-write @@ -36798,12 +34673,12 @@ - 16 - 0x1 + 4 + 0x4 PLAIN_MEM[%s] The memory that stores plaintext 0x0 - 0x8 + 0x20 LINESIZE