diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 77dfbf1b..1a2dbacd 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -156,3 +156,27 @@ jobs:
         run: zig build -Doptimize=ReleaseSmall --summary all
         working-directory: examples/${{ matrix.example_dir }}
 
+  stm32-gen-check:
+    name: Check that stm32 generated code is up to date
+    continue-on-error: true
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout code
+        uses: actions/checkout@v3
+      - name: Setup Zig
+        uses: mlugg/setup-zig@v1
+        with:
+          version: ${{ env.ZIG_VERSION }}
+      - name: Generate Code
+        run: zig build update
+        working-directory: port/stmicro/stm32
+      - name: Check for code diffs
+        run: |
+          if [[ $(git status --porcelain) ]]; then
+            echo "Code differences detected:"
+            git diff
+            echo "Please commit or fix these changes to proceed."
+            exit 1
+          else
+            echo "No code differences detected."
+          fi
diff --git a/build.zig b/build.zig
index d12da022..d6c01114 100644
--- a/build.zig
+++ b/build.zig
@@ -328,7 +328,7 @@ pub fn MicroBuild(port_select: PortSelect) type {
             cpu_mod.addImport("microzig", core_mod);
             core_mod.addImport("cpu", cpu_mod);
 
-            const regz_exe = b.dependency("tools/regz", .{}).artifact("regz");
+            const regz_exe = b.dependency("tools/regz", .{ .optimize = .ReleaseSafe }).artifact("regz");
             const chip_source = switch (target.chip.register_definition) {
                 .atdf, .svd => |file| blk: {
                     const regz_run = b.addRunArtifact(regz_exe);