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Wide mux cells ($_MUX4_ et al) are incorrectly marked as evaluable #5035

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KrystalDelusion opened this issue Apr 16, 2025 · 1 comment
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@KrystalDelusion
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Version

0.52

On which OS did this happen?

Linux

Reproduction Steps

Run the below script

read_rtlil << EOF
module \gold

  wire input 1 \A
  wire input 2 \B
  wire input 3 \C
  wire input 4 \D
  wire input 5 \S
  wire input 6 \T
  wire output 7 \Y

  cell $_MUX4_ \UUT
    connect \A \A
    connect \B \B
    connect \C \C
    connect \D \D
    connect \S \S
    connect \T \T
    connect \Y \Y
  end
end
EOF

eval -set-undef -table A,S,T

(This isn't a perfect test, since the eval command doesn't actually check is_evaluable and returns values for non evaluable cells such as $_FF_, but it's a close enough proxy for the purposes of this bug report)

Expected Behavior

Should return a result, as with

read_rtlil << EOF
module \gold

  wire input 1 \A
  wire input 2 \B
  wire input 3 \S
  wire output 4 \Y

  cell $_MUX_ \UUT
    connect \A \A
    connect \B \B
    connect \S \S
    connect \Y \Y
  end
end
EOF

eval -set-undef -table A,S

Actual Behavior

Hangs forever.

@KrystalDelusion KrystalDelusion added the pending-verification This issue is pending verification and/or reproduction label Apr 16, 2025
@KrystalDelusion
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Spinning this out from #5024 because I'm not sure what the best way to handle these cells is, given that CellTypes::eval() only supports up to 4 inputs, and muxcover (which creates the wide mux cells) is usually immediately followed by techmapping. So the solution here might instead be to just mark them as not evaluable and be done with it. Alternatively a solution which models them as trees of $_MUX_ cells (i.e. reversing the muxcover) in consteval might also be appropriate.

@KrystalDelusion KrystalDelusion removed the pending-verification This issue is pending verification and/or reproduction label Apr 22, 2025
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