How to write a .blif or .bench without any optimization and only write the combinational parts of the circuits?

[chenxindaaa]

I found a Yosys script that can write .blif, and implement it on an open-source control ac97. The script is as follows:
read_verilog ac97_top.v synth -flatten -top ac97_top async2sync dffunmap abc -g AND write_blif ac97.blif
However, this script can not write the combinational AIG as .blif. So, I write an ABC script named comb.script as follows:
strash write ac97_comb.bench
Then, I add a line in Yosys script:
read_verilog ac97_top.v synth -flatten -top ac97_top async2sync dffunmap abc -g AND -script comb.script write_blif ac97.blif
Finally, I can get a .blif file without DFFs. Is this flow correct? Additionally, I found this flow runs some OPT passes, but I only want the unoptimized AIG. Are these optimizations necessary?

[nakengelhardt]

This does not work. As noted in the documentation for the abc command:

Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to "run ABC on your design". It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as BLIF file with write_blif and then load that into ABC externally if
you want to use ABC to convert your design into another format.

[chenxindaaa]

Appreciate your prompt reply. I want to get combinational parts of a sequential circuit without logic optimization, and then implement custom logic optimization by ABC using these extracted combinational parts as .blif. Could you please help me fix the Yosys script using the example ac97?