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Smartcam: Failed timing checks #9

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shadivl opened this issue Sep 25, 2021 · 2 comments

shadivl commented Sep 25, 2021

Hello! I am trying to build the kv260_ispMipiRx_vcu_DP platform for Smartcam. I am using this manual for this (https://xilinx.github.io/kria-apps-docs/main/build/html/docs/smartcamera/smartcamera_landing.html#tutorials).
I also changed video input from the IAS to the Raspberry Pi connector.
But at the step "Integrating the overlay into the Platform" (https://xilinx.github.io/kria-apps-docs/main/build/html/docs/build_accel.html) the program displays an error message about failed timing one of HLS-core.

What do I need to do to fix it?
runme.log
terminal.txt

Collaborator

sweatharao commented Sep 27, 2021

The timing is quite tight on this design. You can change implementation strategies on the kernel to see if it will meet timing. The strategy is set in the following file.
https://github.com/Xilinx/kv260-vitis/blob/release-2020.2.2_k26/overlays/examples/smartcam/prj_conf/prj_config_1dpu#L44

Contributor

chkohn commented Nov 29, 2022

@shadivl can this issue be closed?

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