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Timing error compiling hello_world with kv260_ispMipiRx_vcu_DP platform #7
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The make options that you have listed don't apply to this repo so not sure what exactly you are running. Maybe this is really something that should be posted in the other git repo instead. I'm not familiar with the accelerator that you are using but timing closure problems can be due to many different things. The examples that are shipped as part of this repo have all been vetted and close timing. So this is really not an "issue" as I can always create a design that does not meet timing on a given device for a given platform. A few debug pointers:
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@chkohn Thank you for your reply. I am using the Can you please clarify if the platforms in this repository are intended to be used with custom kernels in the Vitis acceleration flow, or if they are solely designed to be coupled with the overlays in this repository and Xilinx DPU, purely targeted for development of software applications without changing the platform and PL design? Edit: Can you please also clarify if these platforms in this repository support Dynamic Function eXchange (DFX), which would further complicate routing from what I understand? |
@zohourih the only advice I can give is to look at the generated Vivado design and analyze it to see why timing is not met. If it's a small kernel, then it should definitely be able to meet timing. Some of the provided examples instantiate a DPU IP and a custom preprocessing accelerator and they meet timing. You can also compare the generated Vivado designs of one of the provided overlays with your kernel, it may give you a clue what's different. The platforms are definitely meant to be extended with custom kernels but you may need to tweak clock frequency or settings for the vivado linker to achieve optimal results. Each platform comes with one example overlay which can be used as starting point or reference. None of the provided platforms support DFX today. |
@chkohn Yes, the design is extremely small, and that is why I am surprised it is failing to meet timing. The timing failure is happening with the 300 MHz clock and on the AXI interconnect that is automatically inserted into the design by Vitis to connect the user kernel to HP1. The slack is not too large (-0.040); however, considering the simplicity and small size of the user kernel, even such a small negative slack is quite surprising. I can imagine the designs provided by Xilinx have probably gone through a lot of manual timing tuning, which would incur a lot of burden for normal users if they have to do such thing for even simple and small designs. Nonetheless, I will try to dig deeper and see if I can get around the timing failure. |
@zohourih ok, please share your results here. |
@zohourih can you take a look at this file and use it in your flow
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@zohourih can this issue be closed? |
I have built the
kv260_ispMipiRx_vcu_DP
platform provided in this repository and I am trying to synthesize thehello_world
example from the Vitis Accel repository with this platform. However, the build fails with timing errors. This is my command line:make sd_card TARGET=hw DEVICE=kv260_ispMipiRx_vcu_DP HOST_ARCH=aarch64 EDGE_COMMON_SW=/tools/xilinx/petalinux/2020.2/
And this is the end of the build log:
I have attached the timing summary, as well. Am I doing something wrong here?
dr_timing_summary.txt
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