How to resolve this issue I am getting on Alchitry Labs 1.2.7?

[MShaswat03]

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 42 out of 52 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: customout[2:0], io_dip[2], io_dip[1], io_dip[0], io_led[23:0], io_seg[7:0], and io_sel[3:0]. ERROR: [Vivado 12-13638] Failed runs(s) : 'impl_1'

[sweatharao]

@codesmoker1916 the new IOs you have added customout[2:0], io_dip[2], io_dip[1], io_dip[0], io_led[23:0], io_seg[7:0], and io_sel[3:0] need an FPAG pin location in the xdc file.