create main branch from next branch

sdausr · sdausr · commit a60e1df95fa4 · 2022-10-23T19:53:55.000-06:00
diff --git a/Jenkinsfile b/Jenkinsfile
@@ -1,2 +1,2 @@
 @Library('pipeline-library')_
-FullVitisLibPipeline (branch: 'next', libname: 'Vitis_Libraries', TARGETS: 'hls_csim:hls_csynth:hls_cosim:vivado_syn:vitis_sw_emu:vitis_hw_emu:vitis_hw_build:vitis_aie_sim:vitis_aie_x86sim', TOOLVERSION: '2022.2_stable_latest')
+FullVitisLibPipeline (branch: 'main', libname: 'Vitis_Libraries', TARGETS: 'hls_csim:hls_csynth:hls_cosim:vivado_syn:vitis_sw_emu:vitis_hw_emu:vitis_hw_build:vitis_aie_sim:vitis_aie_x86sim', TOOLVERSION: '2022.2_released')

Original file line number	Diff line number	Diff line change
`@@ -1,2 +1,2 @@`
`1`	`1`	`@Library('pipeline-library')_`
`2`		`-FullVitisLibPipeline (branch: 'next', libname: 'Vitis_Libraries', TARGETS: 'hls_csim:hls_csynth:hls_cosim:vivado_syn:vitis_sw_emu:vitis_hw_emu:vitis_hw_build:vitis_aie_sim:vitis_aie_x86sim', TOOLVERSION: '2022.2_stable_latest')`
	`2`	`+FullVitisLibPipeline (branch: 'main', libname: 'Vitis_Libraries', TARGETS: 'hls_csim:hls_csynth:hls_cosim:vivado_syn:vitis_sw_emu:vitis_hw_emu:vitis_hw_build:vitis_aie_sim:vitis_aie_x86sim', TOOLVERSION: '2022.2_released')`