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Fixed typo.
1 parent d190f9f commit ae14287

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2 files changed

+4
-4
lines changed

2 files changed

+4
-4
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pyVHDLModel/SyntaxModel.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -643,7 +643,7 @@ def AnalyzeDependencies(self) -> None:
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self.IndexPackages()
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self.IndexArchitectures()
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self.LinkInstanziations()
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self.LinkInstantiations()
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self.CreateHierarchyGraph()
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def CreateCompilerOrderGraph(self) -> None:
@@ -959,7 +959,7 @@ def LinkContextReferences(self) -> None:
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designUnit._referencedPackages[libraryIdentifier][packageIdentifier] = package
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962-
def LinkInstanziations(self) -> None:
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def LinkInstantiations(self) -> None:
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for architecture in self.IterateDesignUnits(DesignUnitKind.Architecture):
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for instance in architecture.IterateInstantiations():
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if isinstance(instance, EntityInstantiation):

tests/unit/Analyze.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -198,10 +198,10 @@ def test_IndexArchitectures(self):
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design.IndexArchitectures()
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201-
def test_LinkInstanziations(self):
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def test_LinkInstantiations(self):
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design = self.CreateDesign()
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design.LinkInstanziations()
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design.LinkInstantiations()
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def test_CreateHierarchyGraph(self):
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design = self.CreateDesign()

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