@@ -117,7 +117,7 @@ def set_RP_system_clock(freqHz:int):
117117 machine .freq (int (freqHz ))
118118
119119 @micropython .native
120- def write_input_byte (val ):
120+ def write_ui_in_byte (val ):
121121 # dump_portset('ui_in', val)
122122 # low level machine stuff
123123 # move the value bits to GPIO spots
@@ -131,12 +131,12 @@ def write_input_byte(val):
131131 machine .mem32 [0xd000001c ] = val
132132
133133 @micropython .native
134- def read_input_byte ():
134+ def read_ui_in_byte ():
135135 # just read the high and low nibbles from GPIO and combine into a byte
136136 return ( (machine .mem32 [0xd0000004 ] & (0xf << 17 )) >> (17 - 4 )) | ((machine .mem32 [0xd0000004 ] & (0xf << 9 )) >> 9 )
137137
138138 @micropython .native
139- def write_bidir_byte (val ):
139+ def write_uio_byte (val ):
140140 # dump_portset('uio', val)
141141 # low level machine stuff
142142 # move the value bits to GPIO spots
@@ -151,24 +151,24 @@ def write_bidir_byte(val):
151151
152152
153153 @micropython .native
154- def read_bidir_byte ():
154+ def read_uio_byte ():
155155 return (machine .mem32 [0xd0000004 ] & (0xff << 21 )) >> 21
156156
157157 @micropython .native
158- def read_bidir_outputenable ():
158+ def read_uio_outputenable ():
159159 # GPIO_OE register, masked for our bidir pins
160160 return (machine .mem32 [0xd0000020 ] & 0x1FE00000 ) >> 21
161161
162162
163163 @micropython .native
164- def write_bidir_outputenable (val ):
164+ def write_uio_outputenable (val ):
165165 # dump_portset('uio_oe', val)
166166 # GPIO_OE register, clearing bidir pins and setting any enabled
167167 val = (val << 21 )
168168 machine .mem32 [0xd0000020 ] = (machine .mem32 [0xd0000020 ] & ((1 << 21 ) - 1 )) | val
169169
170170 @micropython .native
171- def write_output_byte (val ):
171+ def write_uo_out_byte (val ):
172172 # dump_portset('uo_out', val)
173173 # low level machine stuff
174174 # move the value bits to GPIO spots
@@ -181,7 +181,7 @@ def write_output_byte(val):
181181 machine .mem32 [0xd000001c ] = val
182182
183183 @micropython .native
184- def read_output_byte ():
184+ def read_uo_out_byte ():
185185
186186 # sample code to deal with differences between
187187 # PCBs, not actually required as we didn't move anything
@@ -228,47 +228,47 @@ def set_RP_system_clock(freqHz:int):
228228 RP2040SystemClockDefaultHz = freqHz
229229
230230 _inbyte = 0
231- def write_input_byte (val ):
231+ def write_ui_in_byte (val ):
232232 global _inbyte
233233 print (f'Sim write_input_byte { val } ' )
234234 _inbyte = val
235235
236- def read_input_byte ():
236+ def read_ui_in_byte ():
237237 print ('Sim read_output_byte' )
238238 return _inbyte
239239
240240
241241 _uio_byte = 0
242- def write_bidir_byte (val ):
242+ def write_uio_byte (val ):
243243 global _uio_byte
244244 print (f'Sim write_bidir_byte { val } ' )
245245 _uio_byte = val
246246
247247
248248
249- def read_bidir_byte ():
249+ def read_uio_byte ():
250250 print ('Sim read_output_byte' )
251251 return _uio_byte
252252
253253 _outbyte = 0
254- def write_output_byte (val ):
254+ def write_uo_out_byte (val ):
255255 global _outbyte
256256 print (f'Sim write_output_byte { val } ' )
257257 _outbyte = val
258258
259- def read_output_byte ():
259+ def read_uo_out_byte ():
260260 global _outbyte
261261 v = _outbyte
262262 #_outbyte += 1
263263 print ('Sim read_output_byte' )
264264 return v
265265
266266 _uio_oe_pico = 0
267- def read_bidir_outputenable ():
267+ def read_uio_outputenable ():
268268 print ('Sim read_bidir_outputenable' )
269269 return _uio_oe_pico
270270
271- def write_bidir_outputenable (val ):
271+ def write_uio_outputenable (val ):
272272 global _uio_oe_pico
273273 print (f'Sim write_bidir_outputenable { val } ' )
274274 _uio_oe_pico = val
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