This design implements a digital down converter that reduces the sampling rate of the input signal to match the desired output sampling rate. In this example we go from 1.5GSPS to 187.5MSPS.
There are two steps in this design. The first step is to tune to the desired frequency of interest using the Numerical Controlled Oscillator (NCO) to generate sin and cosine values for the desired output frequency.
The second step is to down sample the data by configuring the FIR (Vector) block as a decimation filter with a decimation value of '2'. Decimation happens in 3 stages, from 1.5GSPS to 750 MSPS to 375MSPS, and finally to 187.5MSPS.
In this case the SSR parameter is set to 3. This lets 3 data samples to process per PL clock cycle.
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