ignore_pins_on_floorplan

Author: lukasc-ubc

klayout_dot_config/grain.xml

@@ -1,7 +1,7 @@
 <?xml version="1.0" encoding="utf-8"?>
 <salt-grain>
  <name>siepic_tools</name>
- <version>0.5.22</version>
+ <version>0.5.23</version>
  <api-version>0.27</api-version>
  <title>SiEPIC Tools</title>
  <doc>Tools for designing Silicon Photonic Integrated Circuits, including waveguides, component simulations, functional verification, DRC verification, Functional verification, netlist extraction, circuit simulations. Layout can be implemented graphically or by programming in Python using the SiEPIC functions and KLayout Python API. Framework and examples for creating layouts using scripts. Includes a generic PDK (GSiP). Other PDKs are installed separately, and depend on SiEPIC-Tools.</doc>

klayout_dot_config/python/SiEPIC/__init__.py

@@ -2,7 +2,7 @@
 SiEPIC-Tools package for KLayout
 '''
 
-__version__ = "0.5.22"
+__version__ = "0.5.23"
 
 print("KLayout SiEPIC-Tools version %s" %__version__)
 

klayout_dot_config/python/SiEPIC/verification.py

@@ -320,6 +320,27 @@ def layout_check(cell=None, verbose=False, GUI=False, timing=False, file_rdb = N
     else:
         minimum_radius_check = True
 
+    if verification:
+        try:
+            ignore_pins_on_floorplan = eval(
+                verification["verification"]["ignore-pins-on-floorplan"]
+            )
+            layer_floorplan = TECHNOLOGY['FloorPlan']
+            # find the FloorPlan geometry
+            iter = cell.begin_shapes_rec(cell.layout().layer(layer_floorplan))
+            floorplan_boxes = []
+            while not(iter.at_end()):
+                if iter.shape().is_box():
+                    box = iter.shape().box
+                    box2 = iter.shape().box.transformed(iter.itrans())
+                    floorplan_boxes.append(box2)
+                iter.next()
+        except:
+            ignore_pins_on_floorplan = False
+    else:
+        ignore_pins_on_floorplan = False
+        
+
     if verification:
         # define device-only layers
         try:
@@ -442,6 +463,13 @@ def layout_check(cell=None, verbose=False, GUI=False, timing=False, file_rdb = N
             if pin.type == _globals.PIN_TYPES.OPTICAL:
                 if pin.net.idx == None:
                     # disconnected optical pin
+                    
+                    # Check if the pin is touching the floorplan; if so assume it is a port to an adjacent layout and ignore
+                    if ignore_pins_on_floorplan and floorplan_boxes:
+                        if pya.Region(pin.path).interacting(pya.Region(floorplan_boxes[0]).edges()):
+                            print(" - pin touching floorplan, skipping error")
+                            continue
+                    
                     if verbose:
                         print(" - Found disconnected pin, type %s, at (%s)" % (pin.type, pin.center))
                         pin.display()

klayout_dot_config/python/pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "SiEPIC"
-version = "0.5.22"
+version = "0.5.23"
 authors = [
   { name="Lukas Chrostowski", email="[email protected]" },
 ]