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Unified magic number storage? #13
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Thanks @fpistm ! I did some tests on F407 mcu + Arduino IDE 1.8.9 + STM Core, to use the backed register instead of using the battery backed SRAM region.
When I try to write directly to the register address the value I write is saved successfully to the register. This reads successfully the RTC_BKP_DR4 register value I have also successfully wrote the RTC_BKP_DR4 register by directly writing.
Maybe I am missing something ... |
Humm... right strange behaviour. setgetYou can check here how I handle this in the core: I use it for HID bootloader for STM32F1 without any issue on the PR stm32duino/Arduino_Core_STM32#525:
So if HID BL for F4 use the same backup register, I do not need handle specific access across series ;) |
It is not needed to the new HID-BL version. Please, do not upload any code related to the HID-BL to the repo. I have made a lot of changes so far to my local HID-BL copy. When I finish it, we will discuss it and send you a PR. |
Ok. |
Thanks ! |
The LL_RTC_BAK_SetRegister and LL_RTC_BAK_GetRegister did the job ! |
Tests were successful on Bluepill F103 and DIYMROE STM32F407VGT boards |
Nice. Great job @Serasidis |
No change required to the DTR/magic word handling in the core then I guess, magic word still applies to Maple DFU, and DTR will continue to function... |
@BennehBoy , The reboot feature that is based only on DTR signal works ok in both DFU Bootloader 2.0 and HID bootloader as-is (without modifying any bootloader file). For avoiding any malfunction it is better to leave this process as is (with the magic word |
From now on, the |
Hi @Serasidis
First of all, thank you very much for your excellent work!
Currently, STM32F1 handle the magic number thanks the battery backed register (
DR10
):STM32_HID_Bootloader/bootloader_F1/Src/main.c
Line 109 in 717419b
and STM32F4 thanks the battery backed SRAM region at 0.
STM32_HID_Bootloader/bootloader_F4/Src/main.c
Line 138 in 717419b
I wonder if it would not be better to unified them and use only battery backed register which is available across all series while backup SRAM not ?
And in this case, this could use a common
DRx
index across all series,DR4
should be fine.This allow to unified cores support.
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