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RahixRahix
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treewide: Apply changes for new svd2rust API
As avr-device is upgrading to use svd2rust version 0.33.1, there are some significant changes in the generated API. We have to adapt the HAL code to use the new API whereever relevant. This commit was mostly generated using the following command, which adds the parentheses behind each register access to change it from struct-field access to method call. cargo build --message-format json 2>/dev/null \ | jq '.message.children[].spans[] | {file: .file_name, line: .line_start, col: (.text[0].highlight_start - 1), insert: .suggested_replacement}' 2>/dev/null \ | jq -r '"sed -ri '"'"'" + (.line | tostring) + "s/^(.{" + (.col | tostring) + "})/\\1" + .insert + "/'"'"' $(cd ../..; realpath " + .file + ")"' \ | sort | uniq | bash Shell magic for the win :) Beyond this, .bits() had to be converted to .set() where safe accesses are performed.
1 parent 4182fe7 commit 0bd44f0

25 files changed

+381
-381
lines changed

‎avr-hal-generic/src/adc.rs

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -250,17 +250,17 @@ macro_rules! impl_adc {
250250

251251
#[inline]
252252
fn raw_read_adc(&self) -> u16 {
253-
self.adc.read().bits()
253+
self.adc().read().bits()
254254
}
255255

256256
#[inline]
257257
fn raw_is_converting(&self) -> bool {
258-
self.adcsra.read().adsc().bit_is_set()
258+
self.adcsra().read().adsc().bit_is_set()
259259
}
260260

261261
#[inline]
262262
fn raw_start_conversion(&mut self) {
263-
self.adcsra.modify(|_, w| w.adsc().set_bit());
263+
self.adcsra().modify(|_, w| w.adsc().set_bit());
264264
}
265265

266266
#[inline]
@@ -276,7 +276,7 @@ macro_rules! impl_adc {
276276
match channel {
277277
$(
278278
x if x == $pin_channel => {
279-
$(self.$didr.modify(|_, w| w.$didr_method().set_bit());)?
279+
$(self.$didr().modify(|_, w| w.$didr_method().set_bit());)?
280280
}
281281
)+
282282
_ => unreachable!(),
@@ -288,7 +288,7 @@ macro_rules! impl_adc {
288288
match channel {
289289
$(
290290
x if x == $pin_channel => {
291-
$(self.$didr.modify(|_, w| w.$didr_method().clear_bit());)?
291+
$(self.$didr().modify(|_, w| w.$didr_method().clear_bit());)?
292292
}
293293
)+
294294
_ => unreachable!(),

‎avr-hal-generic/src/eeprom.rs

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -159,8 +159,8 @@ macro_rules! impl_eeprom_common {
159159
$set_address
160160
}
161161

162-
self.eecr.write(|w| w.eere().set_bit());
163-
self.eedr.read().bits()
162+
self.eecr().write(|w| w.eere().set_bit());
163+
self.eedr().read().bits()
164164
}
165165
}
166166

@@ -173,8 +173,8 @@ macro_rules! impl_eeprom_common {
173173
}
174174

175175
//Start EEPROM read operation
176-
self.eecr.write(|w| w.eere().set_bit());
177-
let old_value = self.eedr.read().bits();
176+
self.eecr().write(|w| w.eere().set_bit());
177+
let old_value = self.eedr().read().bits();
178178
let diff_mask = old_value ^ data;
179179

180180
// Check if any bits are changed to '1' in the new value.
@@ -184,33 +184,33 @@ macro_rules! impl_eeprom_common {
184184
// Check if any bits in the new value are '0'.
185185
if data != 0xff {
186186
// Now we know that some bits need to be programmed to '0' also.
187-
self.eedr.write(|w| w.bits(data)); // Set EEPROM data register.
187+
self.eedr().write(|w| w.bits(data)); // Set EEPROM data register.
188188

189189
{
190190
let $periph_ewmode_var = &self;
191191
$set_erasewrite_mode
192192
}
193-
self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Erase+Write operation.
193+
self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Erase+Write operation.
194194
} else {
195195
// Now we know that all bits should be erased.
196196
{
197197
let $periph_emode_var = &self;
198198
$set_erase_mode
199199
}
200-
self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Erase-only operation.
200+
self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Erase-only operation.
201201
}
202202
}
203203
//Now we know that _no_ bits need to be erased to '1'.
204204
else {
205205
// Check if any bits are changed from '1' in the old value.
206206
if diff_mask != 0 {
207207
// Now we know that _some_ bits need to the programmed to '0'.
208-
self.eedr.write(|w| w.bits(data)); // Set EEPROM data register.
208+
self.eedr().write(|w| w.bits(data)); // Set EEPROM data register.
209209
{
210210
let $periph_wmode_var = &self;
211211
$set_write_mode
212212
}
213-
self.eecr.modify(|_, w| w.eepe().set_bit()); // Start Write-only operation.
213+
self.eecr().modify(|_, w| w.eepe().set_bit()); // Start Write-only operation.
214214
}
215215
}
216216
}
@@ -229,7 +229,7 @@ macro_rules! impl_eeprom_common {
229229
$set_erase_mode
230230
}
231231
// Start Erase-only operation.
232-
self.eecr.modify(|_, w| w.eepe().set_bit());
232+
self.eecr().modify(|_, w| w.eepe().set_bit());
233233
}
234234
}
235235
}
@@ -249,7 +249,7 @@ macro_rules! impl_eeprom_atmega_old {
249249
#[inline]
250250
pub unsafe fn wait_read(regs: &$EEPROM) {
251251
//Wait for completion of previous write.
252-
while regs.eecr.read().eewe().bit_is_set() {}
252+
while regs.eecr().read().eewe().bit_is_set() {}
253253
}
254254

255255
#[inline]
@@ -268,8 +268,8 @@ macro_rules! impl_eeprom_atmega_old {
268268
unsafe {
269269
atmega_helper::set_address(&self, address);
270270
}
271-
self.eecr.write(|w| w.eere().set_bit());
272-
self.eedr.read().bits()
271+
self.eecr().write(|w| w.eere().set_bit());
272+
self.eedr().read().bits()
273273
}
274274

275275
fn raw_write_byte(&mut self, address: u16, data: u8) {
@@ -278,11 +278,11 @@ macro_rules! impl_eeprom_atmega_old {
278278
}
279279

280280
//Start EEPROM read operation
281-
self.eedr.write(|w| unsafe { w.bits(data) });
281+
self.eedr().write(|w| unsafe { w.bits(data) });
282282

283-
self.eecr.write(|w| w.eemwe().set_bit().eewe().clear_bit());
283+
self.eecr().write(|w| w.eemwe().set_bit().eewe().clear_bit());
284284

285-
self.eecr.write(|w| w.eewe().set_bit());
285+
self.eecr().write(|w| w.eewe().set_bit());
286286
}
287287

288288
fn raw_erase_byte(&mut self, address: u16) {
@@ -305,7 +305,7 @@ macro_rules! impl_eeprom_atmega {
305305
#[inline]
306306
pub unsafe fn wait_read(regs: &$EEPROM) {
307307
//Wait for completion of previous write.
308-
while regs.eecr.read().eepe().bit_is_set() {}
308+
while regs.eecr().read().eepe().bit_is_set() {}
309309
}
310310
#[inline]
311311
pub unsafe fn set_address(regs: &$EEPROM, address: $addrwidth) {
@@ -316,21 +316,21 @@ macro_rules! impl_eeprom_atmega {
316316
}
317317
#[inline]
318318
pub unsafe fn set_erasewrite_mode(regs: &$EEPROM) {
319-
regs.eecr.write(|w| {
319+
regs.eecr().write(|w| {
320320
// Set Master Write Enable bit, and and Erase+Write mode mode..
321321
w.eempe().set_bit().eepm().val_0x00()
322322
})
323323
}
324324
#[inline]
325325
pub unsafe fn set_erase_mode(regs: &$EEPROM) {
326-
regs.eecr.write(|w| {
326+
regs.eecr().write(|w| {
327327
// Set Master Write Enable bit, and Erase-only mode..
328328
w.eempe().set_bit().eepm().val_0x01()
329329
});
330330
}
331331
#[inline]
332332
pub unsafe fn set_write_mode(regs: &$EEPROM) {
333-
regs.eecr.write(|w| {
333+
regs.eecr().write(|w| {
334334
// Set Master Write Enable bit, and Write-only mode..
335335
w.eempe().set_bit().eepm().val_0x02()
336336
});
@@ -362,7 +362,7 @@ macro_rules! impl_eeprom_attiny {
362362
mod attiny_helper {
363363
#[inline]
364364
pub unsafe fn wait_read(regs: &$EEPROM) {
365-
while regs.eecr.read().eepe().bit_is_set() {}
365+
while regs.eecr().read().eepe().bit_is_set() {}
366366
}
367367
#[inline]
368368
pub unsafe fn set_address(regs: &$EEPROM, address: $addrwidth) {
@@ -373,21 +373,21 @@ macro_rules! impl_eeprom_attiny {
373373
}
374374
#[inline]
375375
pub unsafe fn set_erasewrite_mode(regs: &$EEPROM) {
376-
regs.eecr.write(|w| {
376+
regs.eecr().write(|w| {
377377
// Set Master Write Enable bit...and and Erase+Write mode mode..
378378
w.eempe().set_bit().eepm().atomic()
379379
});
380380
}
381381
#[inline]
382382
pub unsafe fn set_erase_mode(regs: &$EEPROM) {
383-
regs.eecr.write(|w| {
383+
regs.eecr().write(|w| {
384384
// Set Master Write Enable bit, and Erase-only mode..
385385
w.eempe().set_bit().eepm().erase()
386386
});
387387
}
388388
#[inline]
389389
pub unsafe fn set_write_mode(regs: &$EEPROM) {
390-
regs.eecr.write(|w| {
390+
regs.eecr().write(|w| {
391391
// Set Master Write Enable bit, and Write-only mode..
392392
w.eempe().set_bit().eepm().write()
393393
});

‎avr-hal-generic/src/i2c.rs

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -466,22 +466,22 @@ macro_rules! impl_i2c_twi {
466466
fn raw_setup<CLOCK: $crate::clock::Clock>(&mut self, speed: u32) {
467467
// Calculate TWBR register value
468468
let twbr = ((CLOCK::FREQ / speed) - 16) / 2;
469-
self.twbr.write(|w| unsafe { w.bits(twbr as u8) });
469+
self.twbr().write(|w| unsafe { w.bits(twbr as u8) });
470470

471471
// Disable prescaler
472-
self.twsr.write(|w| w.twps().prescaler_1());
472+
self.twsr().write(|w| w.twps().prescaler_1());
473473
}
474474

475475
#[inline]
476476
fn raw_start(&mut self, address: u8, direction: Direction) -> Result<(), Error> {
477477
// Write start condition
478-
self.twcr
478+
self.twcr()
479479
.write(|w| w.twen().set_bit().twint().set_bit().twsta().set_bit());
480480
// wait()
481-
while self.twcr.read().twint().bit_is_clear() {}
481+
while self.twcr().read().twint().bit_is_clear() {}
482482

483483
// Validate status
484-
match self.twsr.read().tws().bits() {
484+
match self.twsr().read().tws().bits() {
485485
$crate::i2c::twi_status::TW_START | $crate::i2c::twi_status::TW_REP_START => (),
486486
$crate::i2c::twi_status::TW_MT_ARB_LOST
487487
| $crate::i2c::twi_status::TW_MR_ARB_LOST => {
@@ -502,13 +502,13 @@ macro_rules! impl_i2c_twi {
502502
0
503503
};
504504
let rawaddr = (address << 1) | dirbit;
505-
self.twdr.write(|w| unsafe { w.bits(rawaddr) });
505+
self.twdr().write(|w| unsafe { w.bits(rawaddr) });
506506
// transact()
507-
self.twcr.write(|w| w.twen().set_bit().twint().set_bit());
508-
while self.twcr.read().twint().bit_is_clear() {}
507+
self.twcr().write(|w| w.twen().set_bit().twint().set_bit());
508+
while self.twcr().read().twint().bit_is_clear() {}
509509

510510
// Check if the slave responded
511-
match self.twsr.read().tws().bits() {
511+
match self.twsr().read().tws().bits() {
512512
$crate::i2c::twi_status::TW_MT_SLA_ACK
513513
| $crate::i2c::twi_status::TW_MR_SLA_ACK => (),
514514
$crate::i2c::twi_status::TW_MT_SLA_NACK
@@ -535,12 +535,12 @@ macro_rules! impl_i2c_twi {
535535
#[inline]
536536
fn raw_write(&mut self, bytes: &[u8]) -> Result<(), Error> {
537537
for byte in bytes {
538-
self.twdr.write(|w| unsafe { w.bits(*byte) });
538+
self.twdr().write(|w| unsafe { w.bits(*byte) });
539539
// transact()
540-
self.twcr.write(|w| w.twen().set_bit().twint().set_bit());
541-
while self.twcr.read().twint().bit_is_clear() {}
540+
self.twcr().write(|w| w.twen().set_bit().twint().set_bit());
541+
while self.twcr().read().twint().bit_is_clear() {}
542542

543-
match self.twsr.read().tws().bits() {
543+
match self.twsr().read().tws().bits() {
544544
$crate::i2c::twi_status::TW_MT_DATA_ACK => (),
545545
$crate::i2c::twi_status::TW_MT_DATA_NACK => {
546546
self.raw_stop()?;
@@ -565,17 +565,17 @@ macro_rules! impl_i2c_twi {
565565
let last = buffer.len() - 1;
566566
for (i, byte) in buffer.iter_mut().enumerate() {
567567
if i != last {
568-
self.twcr
568+
self.twcr()
569569
.write(|w| w.twint().set_bit().twen().set_bit().twea().set_bit());
570570
// wait()
571-
while self.twcr.read().twint().bit_is_clear() {}
571+
while self.twcr().read().twint().bit_is_clear() {}
572572
} else {
573-
self.twcr.write(|w| w.twint().set_bit().twen().set_bit());
573+
self.twcr().write(|w| w.twint().set_bit().twen().set_bit());
574574
// wait()
575-
while self.twcr.read().twint().bit_is_clear() {}
575+
while self.twcr().read().twint().bit_is_clear() {}
576576
}
577577

578-
match self.twsr.read().tws().bits() {
578+
match self.twsr().read().tws().bits() {
579579
$crate::i2c::twi_status::TW_MR_DATA_ACK
580580
| $crate::i2c::twi_status::TW_MR_DATA_NACK => (),
581581
$crate::i2c::twi_status::TW_MR_ARB_LOST => {
@@ -589,14 +589,14 @@ macro_rules! impl_i2c_twi {
589589
}
590590
}
591591

592-
*byte = self.twdr.read().bits();
592+
*byte = self.twdr().read().bits();
593593
}
594594
Ok(())
595595
}
596596

597597
#[inline]
598598
fn raw_stop(&mut self) -> Result<(), Error> {
599-
self.twcr
599+
self.twcr()
600600
.write(|w| w.twen().set_bit().twint().set_bit().twsto().set_bit());
601601
Ok(())
602602
}

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