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jgreenhalgh-armJames Greenhalgh
jgreenhalgh-arm
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James Greenhalgh
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[AArch64] Improve arm_neon.h vml<as>_lane handling.
gcc/ * config/aarch64/aarch64-simd-builtins.def (fma): New. * config/aarch64/aarch64-simd.md (aarch64_mla_elt<mode>): New. (aarch64_mla_elt_<vswap_width_name><mode>): Likewise. (aarch64_mls_elt<mode>): Likewise. (aarch64_mls_elt_<vswap_width_name><mode>): Likewise. (aarch64_fma4_elt<mode>): Likewise. (aarch64_fma4_elt_<vswap_width_name><mode>): Likewise. (aarch64_fma4_elt_to_128v2df): Likewise. (aarch64_fma4_elt_to_64df): Likewise. (fnma<mode>4): Likewise. (aarch64_fnma4_elt<mode>): Likewise. (aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise. (aarch64_fnma4_elt_to_128v2df): Likewise. (aarch64_fnma4_elt_to_64df): Likewise. * config/aarch64/iterators.md (VDQSF): New. * config/aarch64/arm_neon.h (vfm<as><sdq>_lane<q>_f<32, 64>): Convert to C implementation. (vml<sa><q>_lane<q>_<fsu><16, 32, 64>): Likewise. gcc/testsuite/ * gcc.target/aarch64/fmla-intrinsic.c: New. * gcc.target/aarch64/mla-intrinsic.c: Likewise. * gcc.target/aarch64/fmls-intrinsic.c: Likewise. * gcc.target/aarch64/mls-intrinsic.c: Likewise. From-SVN: r202625
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‎gcc/ChangeLog

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2013-09-16 James Greenhalgh <[email protected]>
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* config/aarch64/aarch64-simd-builtins.def (fma): New.
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* config/aarch64/aarch64-simd.md
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(aarch64_mla_elt<mode>): New.
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(aarch64_mla_elt_<vswap_width_name><mode>): Likewise.
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(aarch64_mls_elt<mode>): Likewise.
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(aarch64_mls_elt_<vswap_width_name><mode>): Likewise.
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(aarch64_fma4_elt<mode>): Likewise.
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(aarch64_fma4_elt_<vswap_width_name><mode>): Likewise.
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(aarch64_fma4_elt_to_128v2df): Likewise.
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(aarch64_fma4_elt_to_64df): Likewise.
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(fnma<mode>4): Likewise.
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(aarch64_fnma4_elt<mode>): Likewise.
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(aarch64_fnma4_elt_<vswap_width_name><mode>): Likewise.
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(aarch64_fnma4_elt_to_128v2df): Likewise.
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(aarch64_fnma4_elt_to_64df): Likewise.
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* config/aarch64/iterators.md (VDQSF): New.
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* config/aarch64/arm_neon.h
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(vfm<as><sdq>_lane<q>_f<32, 64>): Convert to C implementation.
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(vml<sa><q>_lane<q>_<fsu><16, 32, 64>): Likewise.
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2013-09-16 James Greenhalgh <[email protected]>
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* config/aarch64/aarch64-simd.md (aarch64_mul3_elt<mode>): New.

‎gcc/config/aarch64/aarch64-simd-builtins.def

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/* Implemented by aarch64_st1<VALL:mode>. */
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BUILTIN_VALL (STORE1, st1, 0)
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/* Implemented by fma<mode>4. */
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BUILTIN_VDQF (TERNOP, fma, 4)
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‎gcc/config/aarch64/aarch64-simd.md

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@@ -1070,6 +1070,38 @@
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_mla_elt<mode>"
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(plus:VDQHS
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(mult:VDQHS
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(vec_duplicate:VDQHS
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(vec_select:<VEL>
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(match_operand:VDQHS 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQHS 3 "register_operand" "w"))
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(match_operand:VDQHS 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_mla")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_mla_elt_<vswap_width_name><mode>"
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(plus:VDQHS
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(mult:VDQHS
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(vec_duplicate:VDQHS
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(vec_select:<VEL>
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(match_operand:<VSWAP_WIDTH> 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQHS 3 "register_operand" "w"))
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(match_operand:VDQHS 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"mla\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_mla")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "aarch64_mls<mode>"
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[(set (match_operand:VQ_S 0 "register_operand" "=w")
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(minus:VQ_S (match_operand:VQ_S 1 "register_operand" "0")
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(set_attr "simd_mode" "<MODE>")]
10821114
)
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(define_insn "*aarch64_mls_elt<mode>"
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(minus:VDQHS
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(match_operand:VDQHS 4 "register_operand" "0")
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(mult:VDQHS
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(vec_duplicate:VDQHS
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(vec_select:<VEL>
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(match_operand:VDQHS 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQHS 3 "register_operand" "w"))))]
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"TARGET_SIMD"
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"mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_mla")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_mls_elt_<vswap_width_name><mode>"
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[(set (match_operand:VDQHS 0 "register_operand" "=w")
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(minus:VDQHS
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(match_operand:VDQHS 4 "register_operand" "0")
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(mult:VDQHS
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(vec_duplicate:VDQHS
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(vec_select:<VEL>
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(match_operand:<VSWAP_WIDTH> 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQHS 3 "register_operand" "w"))))]
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"TARGET_SIMD"
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"mls\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_mla")
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(set_attr "simd_mode" "<MODE>")]
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)
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;; Max/Min operations.
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(define_insn "<su><maxmin><mode>3"
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[(set (match_operand:VQ_S 0 "register_operand" "=w")
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(set_attr "simd_mode" "<MODE>")]
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)
14851549

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(define_insn "*aarch64_fma4_elt<mode>"
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[(set (match_operand:VDQF 0 "register_operand" "=w")
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(fma:VDQF
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(vec_duplicate:VDQF
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(vec_select:<VEL>
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(match_operand:VDQF 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQF 3 "register_operand" "w")
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(match_operand:VDQF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fma4_elt_<vswap_width_name><mode>"
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[(set (match_operand:VDQSF 0 "register_operand" "=w")
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(fma:VDQSF
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(vec_duplicate:VDQSF
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(vec_select:<VEL>
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(match_operand:<VSWAP_WIDTH> 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQSF 3 "register_operand" "w")
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(match_operand:VDQSF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fma4_elt_to_128df"
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[(set (match_operand:V2DF 0 "register_operand" "=w")
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(fma:V2DF
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(vec_duplicate:V2DF
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(match_operand:DF 1 "register_operand" "w"))
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(match_operand:V2DF 2 "register_operand" "w")
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(match_operand:V2DF 3 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.2d, %2.2d, %1.2d[0]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "V2DF")]
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)
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(define_insn "*aarch64_fma4_elt_to_64v2df"
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[(set (match_operand:DF 0 "register_operand" "=w")
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(fma:DF
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(vec_select:DF
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(match_operand:V2DF 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand")]))
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(match_operand:DF 3 "register_operand" "w")
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(match_operand:DF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmla\\t%0.2d, %3.2d, %1.2d[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "V2DF")]
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)
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(define_insn "fnma<mode>4"
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[(set (match_operand:VDQF 0 "register_operand" "=w")
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(fma:VDQF
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(match_operand:VDQF 1 "register_operand" "w")
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(neg:VDQF
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(match_operand:VDQF 2 "register_operand" "w"))
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(match_operand:VDQF 3 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
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[(set_attr "simd_type" "simd_fmla")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fnma4_elt<mode>"
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[(set (match_operand:VDQF 0 "register_operand" "=w")
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(fma:VDQF
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(neg:VDQF
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(match_operand:VDQF 3 "register_operand" "w"))
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(vec_duplicate:VDQF
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(vec_select:<VEL>
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(match_operand:VDQF 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fnma4_elt_<vswap_width_name><mode>"
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[(set (match_operand:VDQSF 0 "register_operand" "=w")
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(fma:VDQSF
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(neg:VDQSF
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(match_operand:VDQSF 3 "register_operand" "w"))
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(vec_duplicate:VDQSF
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(vec_select:<VEL>
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(match_operand:<VSWAP_WIDTH> 1 "register_operand" "<h_con>")
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(parallel [(match_operand:SI 2 "immediate_operand")])))
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(match_operand:VDQSF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.<Vtype>, %3.<Vtype>, %1.<Vtype>[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "<MODE>")]
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)
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(define_insn "*aarch64_fnma4_elt_to_128df"
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[(set (match_operand:V2DF 0 "register_operand" "=w")
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(fma:V2DF
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(neg:V2DF
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(match_operand:V2DF 2 "register_operand" "w"))
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(vec_duplicate:V2DF
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(match_operand:DF 1 "register_operand" "w"))
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(match_operand:V2DF 3 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.2d, %2.2d, %1.2d[0]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "V2DF")]
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)
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(define_insn "*aarch64_fnma4_elt_to_64v2df"
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[(set (match_operand:DF 0 "register_operand" "=w")
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(fma:DF
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(vec_select:DF
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(match_operand:V2DF 1 "register_operand" "w")
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(parallel [(match_operand:SI 2 "immediate_operand")]))
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(neg:DF
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(match_operand:DF 3 "register_operand" "w"))
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(match_operand:DF 4 "register_operand" "0")))]
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"TARGET_SIMD"
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"fmls\\t%0.2d, %3.2d, %1.2d[%2]"
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[(set_attr "simd_type" "simd_fmla_elt")
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(set_attr "simd_mode" "V2DF")]
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)
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14861681
;; Vector versions of the floating-point frint patterns.
14871682
;; Expands to btrunc, ceil, floor, nearbyint, rint, round.
14881683
(define_insn "<frint_pattern><mode>2"

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