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Kyrylo TkachovKyrylo Tkachov
Kyrylo Tkachov
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Kyrylo Tkachov
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constraints.md (Pd): Allow TARGET_THUMB instead of TARGET_THUMB1.
2013-07-22 Kyrylo Tkachov <[email protected]> * config/arm/constraints.md (Pd): Allow TARGET_THUMB instead of TARGET_THUMB1. (Pz): New constraint. * config/arm/arm.md (arm_addsi3): Add alternatives for 16-bit encodings. (compare_negsi_si): Likewise. (compare_addsi2_op0): Likewise. (compare_addsi2_op1): Likewise. (addsi3_carryin_<optab>): Likewise. (addsi3_carryin_alt2_<optab>): Likewise. (addsi3_carryin_shift_<optab>): Disable cond_exec variant for arm_restrict_it. (subsi3_carryin): Likewise. (arm_subsi3_insn): Add alternatives for 16-bit encoding. (minmax_arithsi): Disable for arm_restrict_it. (minmax_arithsi_non_canon): Adjust for arm_restrict_it. (satsi_<SAT:code>): Disable cond_exec variant for arm_restrict_it. (satsi_<SAT:code>_shift): Likewise. (arm_shiftsi3): Add alternative for 16-bit encoding. (arm32_movhf): Disable for arm_restrict_it. (arm_cmpdi_unsigned): Add alternatives for 16-bit encoding. (arm_movtas_ze): Disable cond_exec variant for arm_restrict_it. From-SVN: r201126
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‎gcc/ChangeLog

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,28 @@
1+
2013-07-22 Kyrylo Tkachov <[email protected]>
2+
3+
* config/arm/constraints.md (Pd): Allow TARGET_THUMB
4+
instead of TARGET_THUMB1.
5+
(Pz): New constraint.
6+
* config/arm/arm.md (arm_addsi3): Add alternatives for 16-bit
7+
encodings.
8+
(compare_negsi_si): Likewise.
9+
(compare_addsi2_op0): Likewise.
10+
(compare_addsi2_op1): Likewise.
11+
(addsi3_carryin_<optab>): Likewise.
12+
(addsi3_carryin_alt2_<optab>): Likewise.
13+
(addsi3_carryin_shift_<optab>): Disable cond_exec variant
14+
for arm_restrict_it.
15+
(subsi3_carryin): Likewise.
16+
(arm_subsi3_insn): Add alternatives for 16-bit encoding.
17+
(minmax_arithsi): Disable for arm_restrict_it.
18+
(minmax_arithsi_non_canon): Adjust for arm_restrict_it.
19+
(satsi_<SAT:code>): Disable cond_exec variant for arm_restrict_it.
20+
(satsi_<SAT:code>_shift): Likewise.
21+
(arm_shiftsi3): Add alternative for 16-bit encoding.
22+
(arm32_movhf): Disable for arm_restrict_it.
23+
(arm_cmpdi_unsigned): Add alternatives for 16-bit encoding.
24+
(arm_movtas_ze): Disable cond_exec variant for arm_restrict_it.
25+
126
2013-07-22 Sofiane Naci <[email protected]>
227

328
* config/arm/arm.md (attribute "insn"): Delete.

‎gcc/config/arm/arm.md

Lines changed: 96 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -953,13 +953,16 @@
953953
;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will
954954
;; put the duplicated register first, and not try the commutative version.
955955
(define_insn_and_split "*arm_addsi3"
956-
[(set (match_operand:SI 0 "s_register_operand" "=rk, r,k, r,r, k, r, k,k,r, k, r")
957-
(plus:SI (match_operand:SI 1 "s_register_operand" "%0, rk,k, r,rk,k, rk,k,r,rk,k, rk")
958-
(match_operand:SI 2 "reg_or_int_operand" "rk, rI,rI,k,Pj,Pj,L, L,L,PJ,PJ,?n")))]
956+
[(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r")
957+
(plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk")
958+
(match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))]
959959
"TARGET_32BIT"
960960
"@
961961
add%?\\t%0, %0, %2
962962
add%?\\t%0, %1, %2
963+
add%?\\t%0, %2
964+
add%?\\t%0, %1, %2
965+
add%?\\t%0, %1, %2
963966
add%?\\t%0, %1, %2
964967
add%?\\t%0, %2, %1
965968
addw%?\\t%0, %1, %2
@@ -981,9 +984,10 @@
981984
operands[1], 0);
982985
DONE;
983986
"
984-
[(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,16")
987+
[(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16")
985988
(set_attr "predicable" "yes")
986-
(set_attr "arch" "t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
989+
(set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no")
990+
(set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*")
987991
(set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
988992
(const_string "arlo_imm")
989993
(const_string "arlo_reg")))
@@ -1090,12 +1094,15 @@
10901094
(define_insn "*compare_negsi_si"
10911095
[(set (reg:CC_Z CC_REGNUM)
10921096
(compare:CC_Z
1093-
(neg:SI (match_operand:SI 0 "s_register_operand" "r"))
1094-
(match_operand:SI 1 "s_register_operand" "r")))]
1097+
(neg:SI (match_operand:SI 0 "s_register_operand" "l,r"))
1098+
(match_operand:SI 1 "s_register_operand" "l,r")))]
10951099
"TARGET_32BIT"
10961100
"cmn%?\\t%1, %0"
10971101
[(set_attr "conds" "set")
1098-
(set_attr "predicable" "yes")]
1102+
(set_attr "predicable" "yes")
1103+
(set_attr "arch" "t2,*")
1104+
(set_attr "length" "2,4")
1105+
(set_attr "predicable_short_it" "yes,no")]
10991106
)
11001107

11011108
;; This is the canonicalization of addsi3_compare0_for_combiner when the
@@ -1192,60 +1199,79 @@
11921199

11931200
(define_insn "*compare_addsi2_op0"
11941201
[(set (reg:CC_C CC_REGNUM)
1195-
(compare:CC_C
1196-
(plus:SI (match_operand:SI 0 "s_register_operand" "r,r,r")
1197-
(match_operand:SI 1 "arm_add_operand" "I,L,r"))
1198-
(match_dup 0)))]
1202+
(compare:CC_C
1203+
(plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r")
1204+
(match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r"))
1205+
(match_dup 0)))]
11991206
"TARGET_32BIT"
12001207
"@
1208+
cmp%?\\t%0, #%n1
1209+
cmn%?\\t%0, %1
12011210
cmn%?\\t%0, %1
12021211
cmp%?\\t%0, #%n1
12031212
cmn%?\\t%0, %1"
12041213
[(set_attr "conds" "set")
12051214
(set_attr "predicable" "yes")
1206-
(set_attr "type" "arlo_imm,arlo_imm,*")]
1215+
(set_attr "arch" "t2,t2,*,*,*")
1216+
(set_attr "predicable_short_it" "yes,yes,no,no,no")
1217+
(set_attr "length" "2,2,4,4,4")
1218+
(set_attr "type" "arlo_imm,*,arlo_imm,arlo_imm,*")]
12071219
)
12081220

12091221
(define_insn "*compare_addsi2_op1"
12101222
[(set (reg:CC_C CC_REGNUM)
1211-
(compare:CC_C
1212-
(plus:SI (match_operand:SI 0 "s_register_operand" "r,r,r")
1213-
(match_operand:SI 1 "arm_add_operand" "I,L,r"))
1214-
(match_dup 1)))]
1223+
(compare:CC_C
1224+
(plus:SI (match_operand:SI 0 "s_register_operand" "l,l,r,r,r")
1225+
(match_operand:SI 1 "arm_add_operand" "Pv,l,I,L,r"))
1226+
(match_dup 1)))]
12151227
"TARGET_32BIT"
12161228
"@
1229+
cmp%?\\t%0, #%n1
1230+
cmn%?\\t%0, %1
12171231
cmn%?\\t%0, %1
12181232
cmp%?\\t%0, #%n1
12191233
cmn%?\\t%0, %1"
12201234
[(set_attr "conds" "set")
12211235
(set_attr "predicable" "yes")
1222-
(set_attr "type" "arlo_imm,arlo_imm,*")]
1223-
)
1236+
(set_attr "arch" "t2,t2,*,*,*")
1237+
(set_attr "predicable_short_it" "yes,yes,no,no,no")
1238+
(set_attr "length" "2,2,4,4,4")
1239+
(set_attr "type"
1240+
"arlo_imm,*,arlo_imm,arlo_imm,*")]
1241+
)
12241242

12251243
(define_insn "*addsi3_carryin_<optab>"
1226-
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
1227-
(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r,r")
1228-
(match_operand:SI 2 "arm_not_operand" "rI,K"))
1229-
(LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
1244+
[(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
1245+
(plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%l,r,r")
1246+
(match_operand:SI 2 "arm_not_operand" "0,rI,K"))
1247+
(LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))))]
12301248
"TARGET_32BIT"
12311249
"@
1250+
adc%?\\t%0, %1
12321251
adc%?\\t%0, %1, %2
12331252
sbc%?\\t%0, %1, #%B2"
12341253
[(set_attr "conds" "use")
1235-
(set_attr "predicable" "yes")]
1254+
(set_attr "predicable" "yes")
1255+
(set_attr "arch" "t2,*,*")
1256+
(set_attr "length" "4")
1257+
(set_attr "predicable_short_it" "yes,no,no")]
12361258
)
12371259

12381260
(define_insn "*addsi3_carryin_alt2_<optab>"
1239-
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
1240-
(plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
1241-
(match_operand:SI 1 "s_register_operand" "%r,r"))
1242-
(match_operand:SI 2 "arm_rhs_operand" "rI,K")))]
1261+
[(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
1262+
(plus:SI (plus:SI (LTUGEU:SI (reg:<cnb> CC_REGNUM) (const_int 0))
1263+
(match_operand:SI 1 "s_register_operand" "%l,r,r"))
1264+
(match_operand:SI 2 "arm_rhs_operand" "l,rI,K")))]
12431265
"TARGET_32BIT"
12441266
"@
1267+
adc%?\\t%0, %1
12451268
adc%?\\t%0, %1, %2
12461269
sbc%?\\t%0, %1, #%B2"
12471270
[(set_attr "conds" "use")
1248-
(set_attr "predicable" "yes")]
1271+
(set_attr "predicable" "yes")
1272+
(set_attr "arch" "t2,*,*")
1273+
(set_attr "length" "4")
1274+
(set_attr "predicable_short_it" "yes,no,no")]
12491275
)
12501276

12511277
(define_insn "*addsi3_carryin_shift_<optab>"
@@ -1260,6 +1286,7 @@
12601286
"adc%?\\t%0, %1, %3%S2"
12611287
[(set_attr "conds" "use")
12621288
(set_attr "predicable" "yes")
1289+
(set_attr "predicable_short_it" "no")
12631290
(set (attr "type") (if_then_else (match_operand 4 "const_int_operand" "")
12641291
(const_string "arlo_shift")
12651292
(const_string "arlo_shift_reg")))]
@@ -1287,7 +1314,8 @@
12871314
rsc%?\\t%0, %2, %1"
12881315
[(set_attr "conds" "use")
12891316
(set_attr "arch" "*,a")
1290-
(set_attr "predicable" "yes")]
1317+
(set_attr "predicable" "yes")
1318+
(set_attr "predicable_short_it" "no")]
12911319
)
12921320

12931321
(define_insn "*subsi3_carryin_const"
@@ -1604,11 +1632,15 @@
16041632

16051633
; ??? Check Thumb-2 split length
16061634
(define_insn_and_split "*arm_subsi3_insn"
1607-
[(set (match_operand:SI 0 "s_register_operand" "=r,r,r,rk,r")
1608-
(minus:SI (match_operand:SI 1 "reg_or_int_operand" "rI,r,r,k,?n")
1609-
(match_operand:SI 2 "reg_or_int_operand" "r,I,r,r, r")))]
1635+
[(set (match_operand:SI 0 "s_register_operand" "=l,l ,l ,l ,r ,r,r,rk,r")
1636+
(minus:SI (match_operand:SI 1 "reg_or_int_operand" "l ,0 ,l ,Pz,rI,r,r,k ,?n")
1637+
(match_operand:SI 2 "reg_or_int_operand" "l ,Py,Pd,l ,r ,I,r,r ,r")))]
16101638
"TARGET_32BIT"
16111639
"@
1640+
sub%?\\t%0, %1, %2
1641+
sub%?\\t%0, %2
1642+
sub%?\\t%0, %1, %2
1643+
rsb%?\\t%0, %2, %1
16121644
rsb%?\\t%0, %2, %1
16131645
sub%?\\t%0, %1, %2
16141646
sub%?\\t%0, %1, %2
@@ -1622,9 +1654,11 @@
16221654
INTVAL (operands[1]), operands[0], operands[2], 0);
16231655
DONE;
16241656
"
1625-
[(set_attr "length" "4,4,4,4,16")
1657+
[(set_attr "length" "4,4,4,4,4,4,4,4,16")
1658+
(set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*")
16261659
(set_attr "predicable" "yes")
1627-
(set_attr "type" "*,arlo_imm,*,*,*")]
1660+
(set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no")
1661+
(set_attr "type" "*,*,*,*,arlo_imm,arlo_imm,*,*,arlo_imm")]
16281662
)
16291663

16301664
(define_peephole2
@@ -3943,7 +3977,7 @@
39433977
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])
39443978
(match_operand:SI 1 "s_register_operand" "0,?r")]))
39453979
(clobber (reg:CC CC_REGNUM))]
3946-
"TARGET_32BIT && !arm_eliminable_register (operands[1])"
3980+
"TARGET_32BIT && !arm_eliminable_register (operands[1]) && !arm_restrict_it"
39473981
"*
39483982
{
39493983
enum rtx_code code = GET_CODE (operands[4]);
@@ -3980,14 +4014,15 @@
39804014
; Reject the frame pointer in operand[1], since reloading this after
39814015
; it has been eliminated can cause carnage.
39824016
(define_insn_and_split "*minmax_arithsi_non_canon"
3983-
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
4017+
[(set (match_operand:SI 0 "s_register_operand" "=Ts,Ts")
39844018
(minus:SI
3985-
(match_operand:SI 1 "s_register_operand" "0,?r")
4019+
(match_operand:SI 1 "s_register_operand" "0,?Ts")
39864020
(match_operator:SI 4 "minmax_operator"
3987-
[(match_operand:SI 2 "s_register_operand" "r,r")
3988-
(match_operand:SI 3 "arm_rhs_operand" "rI,rI")])))
4021+
[(match_operand:SI 2 "s_register_operand" "Ts,Ts")
4022+
(match_operand:SI 3 "arm_rhs_operand" "TsI,TsI")])))
39894023
(clobber (reg:CC CC_REGNUM))]
3990-
"TARGET_32BIT && !arm_eliminable_register (operands[1])"
4024+
"TARGET_32BIT && !arm_eliminable_register (operands[1])
4025+
&& !(arm_restrict_it && CONST_INT_P (operands[3]))"
39914026
"#"
39924027
"TARGET_32BIT && !arm_eliminable_register (operands[1]) && reload_completed"
39934028
[(set (reg:CC CC_REGNUM)
@@ -4046,7 +4081,8 @@
40464081
else
40474082
return "usat%?\t%0, %1, %3";
40484083
}
4049-
[(set_attr "predicable" "yes")]
4084+
[(set_attr "predicable" "yes")
4085+
(set_attr "predicable_short_it" "no")]
40504086
)
40514087

40524088
(define_insn "*satsi_<SAT:code>_shift"
@@ -4072,6 +4108,7 @@
40724108
return "usat%?\t%0, %1, %4%S3";
40734109
}
40744110
[(set_attr "predicable" "yes")
4111+
(set_attr "predicable_short_it" "no")
40754112
(set_attr "shift" "3")
40764113
(set_attr "type" "arlo_shift")])
40774114

@@ -4429,15 +4466,18 @@
44294466
)
44304467

44314468
(define_insn "*arm_shiftsi3"
4432-
[(set (match_operand:SI 0 "s_register_operand" "=r,r")
4469+
[(set (match_operand:SI 0 "s_register_operand" "=l,r,r")
44334470
(match_operator:SI 3 "shift_operator"
4434-
[(match_operand:SI 1 "s_register_operand" "r,r")
4435-
(match_operand:SI 2 "reg_or_int_operand" "M,r")]))]
4471+
[(match_operand:SI 1 "s_register_operand" "0,r,r")
4472+
(match_operand:SI 2 "reg_or_int_operand" "l,M,r")]))]
44364473
"TARGET_32BIT"
44374474
"* return arm_output_shift(operands, 0);"
44384475
[(set_attr "predicable" "yes")
4476+
(set_attr "arch" "t2,*,*")
4477+
(set_attr "predicable_short_it" "yes,no,no")
4478+
(set_attr "length" "4")
44394479
(set_attr "shift" "1")
4440-
(set_attr "type" "arlo_shift,arlo_shift_reg")]
4480+
(set_attr "type" "arlo_shift_reg,arlo_shift,arlo_shift_reg")]
44414481
)
44424482

44434483
(define_insn "*shiftsi3_compare"
@@ -7423,7 +7463,7 @@
74237463
(define_insn "*arm32_movhf"
74247464
[(set (match_operand:HF 0 "nonimmediate_operand" "=r,m,r,r")
74257465
(match_operand:HF 1 "general_operand" " m,r,r,F"))]
7426-
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16)
7466+
"TARGET_32BIT && !(TARGET_HARD_FLOAT && TARGET_FP16) && !arm_restrict_it
74277467
&& ( s_register_operand (operands[0], HFmode)
74287468
|| s_register_operand (operands[1], HFmode))"
74297469
"*
@@ -7548,6 +7588,7 @@
75487588
ldr%?\\t%0, %1\\t%@ float
75497589
str%?\\t%1, %0\\t%@ float"
75507590
[(set_attr "predicable" "yes")
7591+
(set_attr "predicable_short_it" "no")
75517592
(set_attr "type" "mov_reg,load1,store1")
75527593
(set_attr "arm_pool_range" "*,4096,*")
75537594
(set_attr "thumb2_pool_range" "*,4094,*")
@@ -8567,8 +8608,9 @@
85678608

85688609
(define_insn_and_split "*arm_cmpdi_unsigned"
85698610
[(set (reg:CC_CZ CC_REGNUM)
8570-
(compare:CC_CZ (match_operand:DI 0 "s_register_operand" "r")
8571-
(match_operand:DI 1 "arm_di_operand" "rDi")))]
8611+
(compare:CC_CZ (match_operand:DI 0 "s_register_operand" "l,r,r")
8612+
(match_operand:DI 1 "arm_di_operand" "Py,r,rDi")))]
8613+
85728614
"TARGET_32BIT"
85738615
"#" ; "cmp\\t%R0, %R1\;it eq\;cmpeq\\t%Q0, %Q1"
85748616
"&& reload_completed"
@@ -8587,7 +8629,9 @@
85878629
operands[1] = gen_lowpart (SImode, operands[1]);
85888630
}
85898631
[(set_attr "conds" "set")
8590-
(set_attr "length" "8")]
8632+
(set_attr "enabled_for_depr_it" "yes,yes,no")
8633+
(set_attr "arch" "t2,t2,*")
8634+
(set_attr "length" "6,6,8")]
85918635
)
85928636

85938637
(define_insn "*arm_cmpdi_zero"
@@ -12621,7 +12665,8 @@
1262112665
"arm_arch_thumb2"
1262212666
"movt%?\t%0, %L1"
1262312667
[(set_attr "predicable" "yes")
12624-
(set_attr "length" "4")]
12668+
(set_attr "predicable_short_it" "no")
12669+
(set_attr "length" "4")]
1262512670
)
1262612671

1262712672
(define_insn "*arm_rev"

‎gcc/config/arm/constraints.md

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -170,9 +170,9 @@
170170
&& ival > 1020 && ival <= 1275")))
171171

172172
(define_constraint "Pd"
173-
"@internal In Thumb-1 state a constant in the range 0 to 7"
173+
"@internal In Thumb state a constant in the range 0 to 7"
174174
(and (match_code "const_int")
175-
(match_test "TARGET_THUMB1 && ival >= 0 && ival <= 7")))
175+
(match_test "TARGET_THUMB && ival >= 0 && ival <= 7")))
176176

177177
(define_constraint "Pe"
178178
"@internal In Thumb-1 state a constant in the range 256 to +510"
@@ -214,6 +214,11 @@
214214
(and (match_code "const_int")
215215
(match_test "TARGET_THUMB2 && ival >= 0 && ival <= 255")))
216216

217+
(define_constraint "Pz"
218+
"@internal In Thumb-2 state the constant 0"
219+
(and (match_code "const_int")
220+
(match_test "TARGET_THUMB2 && (ival == 0)")))
221+
217222
(define_constraint "G"
218223
"In ARM/Thumb-2 state the floating-point constant 0."
219224
(and (match_code "const_double")

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