testcode -> verilogcode

Author: shtaxxx

MANIFEST.in

@@ -1,5 +1,5 @@
 include README.md
 include README.rst
-recursive-include testcode *
 recursive-include tests *
+recursive-include verilogcode *
 recursive-include img *

pyverilog/ast_code_generator/Makefile

@@ -5,7 +5,7 @@ PYTHON=python3
 #OPT=-m cProfile -o profile.rslt
 
 CODEGEN=codegen.py
-SRCS=../../testcode/led.v
+SRCS=../../verilogcode/led.v
 
 .PHONY: codegen
 codegen:

pyverilog/controlflow/Makefile

@@ -8,7 +8,7 @@ ANALYZER=controlflow_analyzer.py
 ACTIVE=active_analyzer.py
 ACTIVERANGE=active_range.py
 
-SRCS=../../testcode/vectoradd.v
+SRCS=../../verilogcode/vectoradd.v
 TOP=-t TOP
 TARGETS=-s "TOP.MEM_A"
 

pyverilog/dataflow/Makefile

@@ -11,7 +11,7 @@ SUBSET=subset.py
 CODEGEN=codegen.py
 GRAPHGEN=graphgen.py
 
-SRCS=../../testcode/vectoradd.v
+SRCS=../../verilogcode/vectoradd.v
 TOP=-t TOP
 TARGETS=-s "TOP.MEM_A"
 

tests/dataflow_test/test_dat_blocking.py

@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/verilogcode/'
 
 expected = """\
 Directive:

tests/dataflow_test/test_dat_case.py

@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/verilogcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \

tests/dataflow_test/test_dat_case_in_func.py

@@ -4,7 +4,7 @@
 from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
 from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
 
-codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/verilogcode/'
 
 expected = """\
 TOP.IN1: TOP_IN1

tests/dataflow_test/test_dat_casex.py

@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/verilogcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \

tests/dataflow_test/test_dat_decimal.py

@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/verilogcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \

tests/dataflow_test/test_dat_decimal_signed.py

@@ -2,7 +2,7 @@
 import sys
 from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
 
-codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/testcode/'
+codedir = os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) + '/verilogcode/'
 
 expected = """\
 (Bind dest:TOP.cnt \