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‎.travis.yml‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,14 +4,16 @@ sudo: false
44

55
python:
66
- 3.7
7+
- 3.8
8+
- 3.9
79

810
addons:
911
apt:
1012
packages:
1113
- iverilog
1214

1315
install:
14-
- pip install pytest pytest-pythonpath jinja2
16+
- pip install pytest pytest-pythonpath jinja2 ply
1517

1618
script:
1719
- python -m pytest tests

‎README.md‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,6 @@ License
1313

1414
Apache License 2.0 (http://www.apache.org/licenses/LICENSE-2.0)
1515

16-
Note that this software package includes PLY-3.4 in "vparser/ply". The license of PLY is BSD.
17-
1816

1917
Publication
2018
==============================
@@ -65,7 +63,7 @@ for pull requests
6563

6664
Please check "CONTRIBUTORS.md" for the contributors who provided pull requests.
6765

68-
Pyverilog uses **pytest** for the integration testing. **When you send a pull request, please include a testing example with pytest.**
66+
Pyverilog uses **pytest** for the integration testing. **When you send a pull request, please include a testing example with pytest.**
6967
To write a testing code, please refer the existing testing examples in "tests" directory.
7068

7169
If the pull request code passes all the tests successfully and has no obvious problem, it will be merged to the *develop* branch by the main committers.
@@ -77,17 +75,18 @@ Installation
7775
Requirements
7876
--------------------
7977

80-
- Python3: 3.6 or later
78+
- Python3: 3.7 or later
8179
- Icarus Verilog: 10.1 or later
8280

8381
```
8482
sudo apt install iverilog
8583
```
8684

8785
- Jinja2: 2.10 or later
86+
- PLY: 3.4 or later
8887

8988
```
90-
pip3 install jinja2
89+
pip3 install jinja2 ply
9190
```
9291

9392
Optional installation for testing

‎examples/example_active_analyzer.py‎

Lines changed: 21 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -7,39 +7,41 @@
77
# the next line can be removed after installation
88
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
99

10-
import pyverilog.utils.version
10+
import pyverilog
1111
import pyverilog.utils.util as util
1212
import pyverilog.controlflow.splitter as splitter
1313
from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
1414
from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
1515
from pyverilog.controlflow.active_analyzer import VerilogActiveConditionAnalyzer
1616

17+
1718
def main():
1819
INFO = "Active condition analyzer"
19-
VERSION = pyverilog.utils.version.VERSION
20+
VERSION = pyverilog.__version__
2021
USAGE = "Usage: python example_active_analyzer.py -t TOPMODULE file ..."
2122

2223
def showVersion():
2324
print(INFO)
2425
print(VERSION)
2526
print(USAGE)
2627
sys.exit()
27-
28+
2829
optparser = OptionParser()
29-
optparser.add_option("-v","--version",action="store_true",dest="showversion",
30-
default=False,help="Show the version")
31-
optparser.add_option("-t","--top",dest="topmodule",
32-
default="TOP",help="Top module, Default=TOP")
33-
optparser.add_option("-s","--search",dest="searchtarget",action="append",
34-
default=[],help="Search Target Signal")
30+
optparser.add_option("-v", "--version", action="store_true", dest="showversion",
31+
default=False, help="Show the version")
32+
optparser.add_option("-t", "--top", dest="topmodule",
33+
default="TOP", help="Top module, Default=TOP")
34+
optparser.add_option("-s", "--search", dest="searchtarget", action="append",
35+
default=[], help="Search Target Signal")
3536
(options, args) = optparser.parse_args()
3637

3738
filelist = args
3839
if options.showversion:
3940
showVersion()
4041

4142
for f in filelist:
42-
if not os.path.exists(f): raise IOError("file not found: " + f)
43+
if not os.path.exists(f):
44+
raise IOError("file not found: " + f)
4345

4446
if len(filelist) == 0:
4547
showVersion()
@@ -58,25 +60,28 @@ def showVersion():
5860
resolved_binddict = optimizer.getResolvedBinddict()
5961
constlist = optimizer.getConstlist()
6062

61-
canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict,
63+
canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict,
6264
resolved_terms, resolved_binddict, constlist)
6365

6466
for target in options.searchtarget:
6567
signal = util.toTermname(target)
6668

67-
active_conditions = canalyzer.getActiveConditions( signal )
69+
active_conditions = canalyzer.getActiveConditions(signal)
6870
#active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_modify )
6971
#active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_unmodify )
7072

7173
print('Active Cases: %s' % signal)
72-
for fsm_sig, active_conditions in sorted(active_conditions.items(), key=lambda x:str(x[0])):
74+
for fsm_sig, active_conditions in sorted(active_conditions.items(), key=lambda x: str(x[0])):
7375
print('FSM: %s' % fsm_sig)
74-
for state, active_condition in sorted(active_conditions, key=lambda x:str(x[0])):
76+
for state, active_condition in sorted(active_conditions, key=lambda x: str(x[0])):
7577
s = []
7678
s.append('state: %d -> ' % state)
77-
if active_condition: s.append(active_condition.tocode())
78-
else: s.append('empty')
79+
if active_condition:
80+
s.append(active_condition.tocode())
81+
else:
82+
s.append('empty')
7983
print(''.join(s))
8084

85+
8186
if __name__ == '__main__':
8287
main()

‎examples/example_active_range.py‎

Lines changed: 24 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -7,38 +7,40 @@
77
# the next line can be removed after installation
88
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
99

10-
import pyverilog.utils.version
10+
import pyverilog
1111
import pyverilog.utils.util as util
1212
from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
1313
from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
1414
from pyverilog.controlflow.active_range import VerilogActiveAnalyzer
1515

16+
1617
def main():
1718
INFO = "Active condition analyzer (Obsoluted)"
18-
VERSION = pyverilog.utils.version.VERSION
19+
VERSION = pyverilog.__version__
1920
USAGE = "Usage: python example_active_range.py -t TOPMODULE file ..."
2021

2122
def showVersion():
2223
print(INFO)
2324
print(VERSION)
2425
print(USAGE)
2526
sys.exit()
26-
27+
2728
optparser = OptionParser()
28-
optparser.add_option("-v","--version",action="store_true",dest="showversion",
29-
default=False,help="Show the version")
30-
optparser.add_option("-t","--top",dest="topmodule",
31-
default="TOP",help="Top module, Default=TOP")
32-
optparser.add_option("-s","--search",dest="searchtarget",action="append",
33-
default=[],help="Search Target Signal")
29+
optparser.add_option("-v", "--version", action="store_true", dest="showversion",
30+
default=False, help="Show the version")
31+
optparser.add_option("-t", "--top", dest="topmodule",
32+
default="TOP", help="Top module, Default=TOP")
33+
optparser.add_option("-s", "--search", dest="searchtarget", action="append",
34+
default=[], help="Search Target Signal")
3435
(options, args) = optparser.parse_args()
3536

3637
filelist = args
3738
if options.showversion:
3839
showVersion()
3940

4041
for f in filelist:
41-
if not os.path.exists(f): raise IOError("file not found: " + f)
42+
if not os.path.exists(f):
43+
raise IOError("file not found: " + f)
4244

4345
if len(filelist) == 0:
4446
showVersion()
@@ -57,27 +59,28 @@ def showVersion():
5759
resolved_binddict = optimizer.getResolvedBinddict()
5860
constlist = optimizer.getConstlist()
5961

60-
aanalyzer = VerilogActiveAnalyzer(options.topmodule, terms, binddict,
62+
aanalyzer = VerilogActiveAnalyzer(options.topmodule, terms, binddict,
6163
resolved_terms, resolved_binddict, constlist)
6264

6365
for target in options.searchtarget:
6466
signal = util.toTermname(target)
6567

6668
print('Active Conditions: %s' % signal)
67-
active_conditions = aanalyzer.getActiveConditions( signal )
68-
print(sorted(active_conditions, key=lambda x:str(x)))
69+
active_conditions = aanalyzer.getActiveConditions(signal)
70+
print(sorted(active_conditions, key=lambda x: str(x)))
6971

7072
print('Changed Conditions')
71-
changed_conditions = aanalyzer.getChangedConditions( signal )
72-
print(sorted(changed_conditions, key=lambda x:str(x)))
73-
73+
changed_conditions = aanalyzer.getChangedConditions(signal)
74+
print(sorted(changed_conditions, key=lambda x: str(x)))
75+
7476
print('Changed Condition Dict')
75-
changed_conditiondict = aanalyzer.getChangedConditionsWithAssignments( signal )
76-
print(sorted(changed_conditiondict.items(), key=lambda x:str(x[0])))
77-
77+
changed_conditiondict = aanalyzer.getChangedConditionsWithAssignments(signal)
78+
print(sorted(changed_conditiondict.items(), key=lambda x: str(x[0])))
79+
7880
print('Unchanged Conditions')
79-
unchanged_conditions = aanalyzer.getUnchangedConditions( signal )
80-
print(sorted(unchanged_conditions, key=lambda x:str(x)))
81+
unchanged_conditions = aanalyzer.getUnchangedConditions(signal)
82+
print(sorted(unchanged_conditions, key=lambda x: str(x)))
83+
8184

8285
if __name__ == '__main__':
8386
main()

‎examples/example_ast_code.py‎

Lines changed: 21 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -9,43 +9,45 @@
99
import pyverilog.vparser.ast as vast
1010
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
1111

12+
1213
def main():
13-
datawid = vast.Parameter( 'DATAWID', vast.Rvalue(vast.IntConst('32')) )
14-
params = vast.Paramlist( [datawid] )
15-
clk = vast.Ioport( vast.Input('CLK') )
16-
rst = vast.Ioport( vast.Input('RST') )
17-
width = vast.Width( vast.IntConst('7'), vast.IntConst('0') )
18-
led = vast.Ioport( vast.Output('led', width=width) )
19-
ports = vast.Portlist( [clk, rst, led] )
20-
21-
width = vast.Width( vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), vast.IntConst('0') )
14+
datawid = vast.Parameter('DATAWID', vast.Rvalue(vast.IntConst('32')))
15+
params = vast.Paramlist([datawid])
16+
clk = vast.Ioport(vast.Input('CLK'))
17+
rst = vast.Ioport(vast.Input('RST'))
18+
width = vast.Width(vast.IntConst('7'), vast.IntConst('0'))
19+
led = vast.Ioport(vast.Output('led', width=width))
20+
ports = vast.Portlist([clk, rst, led])
21+
22+
width = vast.Width(vast.Minus(vast.Identifier('DATAWID'),
23+
vast.IntConst('1')), vast.IntConst('0'))
2224
count = vast.Reg('count', width=width)
2325

2426
assign = vast.Assign(
25-
vast.Lvalue(vast.Identifier('led')),
27+
vast.Lvalue(vast.Identifier('led')),
2628
vast.Rvalue(
2729
vast.Partselect(
28-
vast.Identifier('count'), # count
29-
vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1:
30-
vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8]
30+
vast.Identifier('count'), # count
31+
vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('1')), # [DATAWID-1:
32+
vast.Minus(vast.Identifier('DATAWID'), vast.IntConst('8'))))) # :DATAWID-8]
3133

3234
sens = vast.Sens(vast.Identifier('CLK'), type='posedge')
33-
senslist = vast.SensList([ sens ])
35+
senslist = vast.SensList([sens])
3436

3537
assign_count_true = vast.NonblockingSubstitution(
3638
vast.Lvalue(vast.Identifier('count')),
3739
vast.Rvalue(vast.IntConst('0')))
38-
if0_true = vast.Block([ assign_count_true ])
40+
if0_true = vast.Block([assign_count_true])
3941

4042
# count + 1
4143
count_plus_1 = vast.Plus(vast.Identifier('count'), vast.IntConst('1'))
4244
assign_count_false = vast.NonblockingSubstitution(
4345
vast.Lvalue(vast.Identifier('count')),
4446
vast.Rvalue(count_plus_1))
45-
if0_false = vast.Block([ assign_count_false ])
47+
if0_false = vast.Block([assign_count_false])
4648

4749
if0 = vast.IfStatement(vast.Identifier('RST'), if0_true, if0_false)
48-
statement = vast.Block([ if0 ])
50+
statement = vast.Block([if0])
4951

5052
always = vast.Always(senslist, statement)
5153

@@ -55,10 +57,11 @@ def main():
5557
items.append(always)
5658

5759
ast = vast.ModuleDef("top", params, ports, items)
58-
60+
5961
codegen = ASTCodeGenerator()
6062
rslt = codegen.visit(ast)
6163
print(rslt)
6264

65+
6366
if __name__ == '__main__':
6467
main()

‎examples/example_codegen.py‎

Lines changed: 13 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -7,36 +7,38 @@
77
# the next line can be removed after installation
88
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
99

10-
import pyverilog.utils.version
10+
import pyverilog
1111
from pyverilog.vparser.parser import VerilogCodeParser
1212
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
1313

14+
1415
def main():
1516
INFO = "Code converter from AST"
16-
VERSION = pyverilog.utils.version.VERSION
17+
VERSION = pyverilog.__version__
1718
USAGE = "Usage: python example_codegen.py file ..."
1819

1920
def showVersion():
2021
print(INFO)
2122
print(VERSION)
2223
print(USAGE)
2324
sys.exit()
24-
25+
2526
optparser = OptionParser()
26-
optparser.add_option("-v","--version",action="store_true",dest="showversion",
27-
default=False,help="Show the version")
28-
optparser.add_option("-I","--include",dest="include",action="append",
29-
default=[],help="Include path")
30-
optparser.add_option("-D",dest="define",action="append",
31-
default=[],help="Macro Definition")
27+
optparser.add_option("-v", "--version", action="store_true", dest="showversion",
28+
default=False, help="Show the version")
29+
optparser.add_option("-I", "--include", dest="include", action="append",
30+
default=[], help="Include path")
31+
optparser.add_option("-D", dest="define", action="append",
32+
default=[], help="Macro Definition")
3233
(options, args) = optparser.parse_args()
3334

3435
filelist = args
3536
if options.showversion:
3637
showVersion()
3738

3839
for f in filelist:
39-
if not os.path.exists(f): raise IOError("file not found: " + f)
40+
if not os.path.exists(f):
41+
raise IOError("file not found: " + f)
4042

4143
if len(filelist) == 0:
4244
showVersion()
@@ -52,5 +54,6 @@ def showVersion():
5254
rslt = codegen.visit(ast)
5355
print(rslt)
5456

57+
5558
if __name__ == '__main__':
5659
main()

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