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README.md
@@ -2,6 +2,7 @@ Pyverilog
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==============================
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[](https://github.com/PyHDI/Pyverilog/actions/workflows/main.yml)
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+[](https://www.travis-ci.com/PyHDI/Pyverilog)
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Python-based Hardware Design Processing Toolkit for Verilog HDL
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