Skip to content

Commit 2a42539

Browse files
committed
Add the travis-c.com badge.
1 parent 190640d commit 2a42539

File tree

1 file changed

+1
-0
lines changed

1 file changed

+1
-0
lines changed

README.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ Pyverilog
22
==============================
33

44
[![CI](https://github.com/PyHDI/Pyverilog/actions/workflows/main.yml/badge.svg)](https://github.com/PyHDI/Pyverilog/actions/workflows/main.yml)
5+
[![Build Status](https://www.travis-ci.com/PyHDI/Pyverilog.svg?branch=develop)](https://www.travis-ci.com/PyHDI/Pyverilog)
56

67
Python-based Hardware Design Processing Toolkit for Verilog HDL
78

0 commit comments

Comments
 (0)