@@ -237,6 +237,17 @@ def make(self, first='cfg', last='bit'):
237237 self ._create_file (self .conf ['tool' ], self .conf ['make_ext' ])
238238 self ._run (self .conf ['make_cmd' ], 'make.log' )
239239
240+ def _get_bitstream (self , bitstream ):
241+ if not bitstream :
242+ for ext in self .conf ['prog_bit' ]:
243+ candidate = Path (self .odir ) / f'{ self .data ["project" ]} .{ ext } '
244+ if candidate .is_file ():
245+ bitstream = candidate
246+ break
247+ if not bitstream or not Path (bitstream ).is_file ():
248+ raise FileNotFoundError (bitstream )
249+ return self ._get_absolute (bitstream , self .conf ['prog_ext' ])
250+
240251 def prog (self , bitstream = None , position = 1 ):
241252 """Program the FPGA
242253
@@ -252,16 +263,7 @@ def prog(self, bitstream=None, position=1):
252263 if position not in range (1 , 9 ):
253264 raise ValueError ('Invalid position.' )
254265 self .logger .info ('Programming' )
255- if not bitstream :
256- for ext in self .conf ['prog_bit' ]:
257- candidate = Path (self .odir ) / f'{ self .data ["project" ]} .{ ext } '
258- if candidate .is_file ():
259- bitstream = candidate
260- break
261- if not bitstream or not Path (bitstream ).is_file ():
262- raise FileNotFoundError (bitstream )
263- bitstream = self ._get_absolute (bitstream , self .conf ['prog_ext' ])
264- self .data ['bitstream' ] = bitstream
266+ self .data ['bitstream' ] = self ._get_bitstream (bitstream )
265267 self .data ['position' ] = position
266268 self ._prog_custom ()
267269 self ._create_file (f'{ self .conf ["tool" ]} -prog' , self .conf ['prog_ext' ])
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