Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

change the length of GPRS, all more control registers #4243

Open
5 tasks done
mlabaf2 opened this issue Feb 4, 2025 · 0 comments
Open
5 tasks done

change the length of GPRS, all more control registers #4243

mlabaf2 opened this issue Feb 4, 2025 · 0 comments
Labels
question Question requiring answer

Comments

@mlabaf2
Copy link

mlabaf2 commented Feb 4, 2025

Before start

  • I have read the RISC-V ISA Manual and this is not a RISC-V ISA question. 我已经阅读过 RISC-V 指令集手册,这不是一个指令集相关的问题。
  • I have read the XiangShan Documents. 我已经阅读过香山文档。
  • I have searched the previous issues and did not find anything relevant. 我已经搜索过之前的 issue,并没有找到相关的。
  • I have searched the previous discussions and did not find anything relevant. 我已经搜索过之前的 discussions,并没有找到相关的。
  • I have reviewed the commit messages from the relevant commit history. 我已经浏览过相关的提交历史和提交信息。

Describe the question

Hi
I want to extent length of GPRs registers to 128 or 129 bits (especially register files for integer section) but I cannot find where is the definition in Xiangshan code, comit a455b9f714df264edb679c81c3d6c74625ea3d82 ? I find len parameter in regfile.scala but cannot find where len is initialize.
also I see genregfile in schaduler.scala, is it the place to specify length of GPRS?
how can I extend length of data bus to support change of register file length?
Also, I cannot find how GPRs are connected to FunctionUnitInput and FuOutput in functionUnit.scala?
thank you for the response

@mlabaf2 mlabaf2 added the question Question requiring answer label Feb 4, 2025
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
question Question requiring answer
Projects
None yet
Development

No branches or pull requests

1 participant