From d97fe952c7d84922b53ddc3940600904ffcf9a1a Mon Sep 17 00:00:00 2001
From: Li Qianruo <liqianruo20s@ict.ac.cn>
Date: Tue, 18 Jun 2024 10:15:25 +0800
Subject: [PATCH] arch-riscv: Fix zero reg RegClass

---
 src/arch/riscv/regs/int.hh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/arch/riscv/regs/int.hh b/src/arch/riscv/regs/int.hh
index bc2857eba6..2c12027f03 100644
--- a/src/arch/riscv/regs/int.hh
+++ b/src/arch/riscv/regs/int.hh
@@ -80,7 +80,7 @@ enum : RegIndex
 };
 
 inline constexpr RegId
-    Zero(IntRegClass, _ZeroIdx),
+    Zero(InvalidRegClass, _ZeroIdx),
     Ra(IntRegClass, _RaIdx),
     Sp(IntRegClass, _SpIdx),
     Gp(IntRegClass, _GpIdx),