lowering: Add micro architecture lowering

Author: flofriday

vadl/main/vadl/ast/Definition.java

@@ -4348,15 +4348,16 @@ enum ProcessKind {
 
 class MicroArchitectureDefinition extends Definition implements IdentifiableNode {
   Identifier id;
-  IsId processor;
+  @Child
+  IsId isa;
   @Child
   List<Definition> definitions;
   SourceLocation loc;
 
-  MicroArchitectureDefinition(Identifier id, IsId processor, List<Definition> definitions,
+  MicroArchitectureDefinition(Identifier id, IsId isa, List<Definition> definitions,
                               SourceLocation loc) {
     this.id = id;
-    this.processor = processor;
+    this.isa = isa;
     this.definitions = definitions;
     this.loc = loc;
   }
@@ -4387,7 +4388,7 @@ void prettyPrint(int indent, StringBuilder builder) {
     builder.append("micro architecture ");
     id.prettyPrint(0, builder);
     builder.append(" implements ");
-    processor.prettyPrint(0, builder);
+    isa.prettyPrint(0, builder);
     builder.append(" = {\n");
     prettyPrintDefinitions(indent + 1, builder, definitions);
     builder.append(prettyIndentString(indent)).append("}\n");
@@ -4403,13 +4404,13 @@ public boolean equals(Object o) {
     }
     MicroArchitectureDefinition that = (MicroArchitectureDefinition) o;
     return Objects.equals(id, that.id)
-        && Objects.equals(processor, that.processor)
+        && Objects.equals(isa, that.isa)
         && Objects.equals(definitions, that.definitions);
   }
 
   @Override
   public int hashCode() {
-    return Objects.hash(id, processor, definitions);
+    return Objects.hash(id, isa, definitions);
   }
 
 }

vadl/main/vadl/ast/MacroExpander.java

@@ -897,7 +897,7 @@ public Definition visit(CpuProcessDefinition definition) {
 
   @Override
   public Definition visit(MicroArchitectureDefinition definition) {
-    return new MicroArchitectureDefinition(definition.id, definition.processor,
+    return new MicroArchitectureDefinition(definition.id, definition.isa,
         expandDefinitions(definition.definitions), copyLoc(definition.loc)
     ).withAnnotations(expandAnnotations(definition.annotations));
   }

vadl/main/vadl/ast/TypeChecker.java

@@ -1876,7 +1876,12 @@ public Void visit(CpuProcessDefinition definition) {
 
   @Override
   public Void visit(MicroArchitectureDefinition definition) {
-    throwUnimplemented(definition);
+    if (!(definition.isa.target() instanceof InstructionSetDefinition)) {
+      throw error("ISA required", definition.isa)
+          .locationDescription(definition.isa, "A MIA implements an ISA but this points to a %s",
+              definition.isa.target().getClass().getSimpleName()).build();
+    }
+    definition.definitions.forEach(this::check);
     return null;
   }
 

vadl/main/vadl/ast/ViamLowering.java

@@ -67,15 +67,19 @@
 import vadl.viam.Function;
 import vadl.viam.Instruction;
 import vadl.viam.InstructionSetArchitecture;
+import vadl.viam.Logic;
 import vadl.viam.Memory;
 import vadl.viam.MemoryRegion;
+import vadl.viam.MicroArchitecture;
 import vadl.viam.PrintableInstruction;
 import vadl.viam.Procedure;
 import vadl.viam.Processor;
 import vadl.viam.PseudoInstruction;
 import vadl.viam.RegisterTensor;
 import vadl.viam.Relocation;
+import vadl.viam.Signal;
 import vadl.viam.Specification;
+import vadl.viam.Stage;
 import vadl.viam.asm.AsmDirectiveMapping;
 import vadl.viam.asm.AsmModifier;
 import vadl.viam.asm.AsmToken;
@@ -1460,8 +1464,30 @@ public Optional<vadl.viam.Definition> visit(MemoryDefinition definition) {
 
   @Override
   public Optional<vadl.viam.Definition> visit(MicroArchitectureDefinition definition) {
-    throw new RuntimeException("The ViamGenerator does not support `%s` yet".formatted(
-        definition.getClass().getSimpleName()));
+    var identifier = generateIdentifier(definition.viamId, definition.identifier());
+    var isa = visitIsa(
+        (InstructionSetDefinition) requireNonNull(definition.isa.target()));
+
+    var children = definition.definitions.stream().map(this::fetch).filter(Optional::isPresent)
+        .map(Optional::orElseThrow).toList();
+    var stages = filterAndCastToInstance(children, Stage.class);
+    var logic = filterAndCastToInstance(children, Logic.class);
+    var signals = filterAndCastToInstance(children, Signal.class);
+    var registers = filterAndCastToInstance(children, RegisterTensor.class);
+    var memories = filterAndCastToInstance(children, Memory.class);
+    var functions = filterAndCastToInstance(children, Function.class);
+
+    return Optional.of(new MicroArchitecture(
+            identifier,
+            isa,
+            stages,
+            logic,
+            signals,
+            registers,
+            memories,
+            functions
+        )
+    );
   }
 
   @Override

vadl/main/vadl/dump/infoEnrichers/RtlEnricherCollection.java

@@ -64,7 +64,7 @@ public class RtlEnricherCollection {
       forType(DefinitionEntity.class, (defEntity, passResults) -> {
         if (defEntity.origin() instanceof MicroArchitecture mia) {
           var mappingExt = mia.extension(MiaMapping.class);
-          var isaExt = mia.processor().isa().extension(InstructionProgressGraphExtension.class);
+          var isaExt = mia.isa().extension(InstructionProgressGraphExtension.class);
           if (mappingExt != null && isaExt != null) {
             var info = InfoUtils.createGraphModal(isaExt.ipg().name, isaExt.ipg().name,
                 viz(isaExt.ipg(), mappingExt));

vadl/main/vadl/viam/MicroArchitecture.java

@@ -26,7 +26,7 @@
  */
 public class MicroArchitecture extends Definition {
 
-  private final Processor processor;
+  private final InstructionSetArchitecture instructionSetArchitecture;
 
   // Stages and Logic elements
   private final List<Stage> stages;
@@ -42,34 +42,39 @@ public class MicroArchitecture extends Definition {
   /**
    * Create a micro architecture definition.
    *
-   * @param identifier identifier
-   * @param processor  processor definition
-   * @param stages     list of stages
-   * @param logic      list of logic elements
+   * @param identifier                 identifier
+   * @param instructionSetArchitecture processor definition
+   * @param stages                     list of stages
+   * @param logic                      list of logic elements
    */
-  public MicroArchitecture(Identifier identifier, Processor processor, List<Stage> stages,
+  public MicroArchitecture(Identifier identifier,
+                           InstructionSetArchitecture instructionSetArchitecture,
+                           List<Stage> stages,
                            List<Logic> logic) {
-    this(identifier, processor, stages, logic, new ArrayList<>(), new ArrayList<>(),
+    this(identifier, instructionSetArchitecture, stages, logic, new ArrayList<>(),
+        new ArrayList<>(),
         new ArrayList<>(), new ArrayList<>());
   }
 
   /**
    * Create a micro architecture definition.
    *
-   * @param identifier identifier
-   * @param processor  processor definition
-   * @param stages     list of stages
-   * @param logic      list of logic elements
-   * @param signals    list of signals
-   * @param registers  list of registers (tensors)
-   * @param memories   list of memories
-   * @param functions  list of functions
+   * @param identifier                 identifier
+   * @param instructionSetArchitecture processor definition
+   * @param stages                     list of stages
+   * @param logic                      list of logic elements
+   * @param signals                    list of signals
+   * @param registers                  list of registers (tensors)
+   * @param memories                   list of memories
+   * @param functions                  list of functions
    */
-  public MicroArchitecture(Identifier identifier, Processor processor, List<Stage> stages,
+  public MicroArchitecture(Identifier identifier,
+                           InstructionSetArchitecture instructionSetArchitecture,
+                           List<Stage> stages,
                            List<Logic> logic, List<Signal> signals, List<RegisterTensor> registers,
                            List<Memory> memories, List<Function> functions) {
     super(identifier);
-    this.processor = processor;
+    this.instructionSetArchitecture = instructionSetArchitecture;
     this.stages = stages;
     this.logic = logic;
     this.signals = signals;
@@ -85,8 +90,8 @@ public MicroArchitecture(Identifier identifier, Processor processor, List<Stage>
     }
   }
 
-  public Processor processor() {
-    return processor;
+  public InstructionSetArchitecture isa() {
+    return instructionSetArchitecture;
   }
 
   public List<Stage> stages() {

vadl/main/vadl/viam/passes/dummyPasses/DummyMiaPass.java

@@ -120,9 +120,9 @@ public PassName getName() {
       return null;
     }
 
-    var mip = viam.processor().orElse(null);
+    var isa = viam.isa().orElse(null);
 
-    if (mip == null) {
+    if (isa == null) {
       // if there is no mip, we just do nothing
       return null;
     }
@@ -144,7 +144,7 @@ public PassName getName() {
 
     var mia = new MicroArchitecture(
         ident,
-        mip,
+        isa,
         new ArrayList<>(List.of(fetch, decode, execute, memory, writeBack)),
         new ArrayList<>(List.of(bypass, predict))
     );

vadl/test/resources/testSource/sys/risc-v/rv32im.vadl

@@ -279,4 +279,9 @@ processor Spike implements RV32IM with ABI = {
   [ base: 0x80000000 ]
   memory region [RAM] DRAM in MEM
 
+}
+
+//[ dataBusWidth : 32 ]
+micro architecture FiveStage implements RV32IM = {
+
 }