OpenCAPI3.0 Reference Design

Author: Joshua-Andersen1

README.md

@@ -7,3 +7,4 @@
 
 # Supported AFUs
 1. AFP
+2. LPC

board_support_packages/ad9v3/ip/create_DLx_PHY_elastic_20.0g.tcl

@@ -0,0 +1,27 @@
+# Generates Transceive IP
+create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -version 1.7 -module_name DLx_phy
+set_property -dict [list CONFIG.CHANNEL_ENABLE {X0Y7 X0Y6 X0Y5 X0Y4 X0Y3 X0Y2 X0Y1 X0Y0} \
+                         CONFIG.TX_MASTER_CHANNEL {X0Y4} \
+                         CONFIG.RX_MASTER_CHANNEL {X0Y4} \
+                         CONFIG.TX_LINE_RATE {20.0} \
+                         CONFIG.TX_PLL_TYPE {QPLL1} \
+                         CONFIG.TX_REFCLK_FREQUENCY {156.25} \
+                         CONFIG.TX_DATA_ENCODING {64B66B} \
+                         CONFIG.TX_OUTCLK_SOURCE {TXPROGDIVCLK} \
+                         CONFIG.RX_LINE_RATE {20.0} \
+                         CONFIG.RX_PLL_TYPE {QPLL1} \
+                         CONFIG.RX_REFCLK_FREQUENCY {156.25} \
+                         CONFIG.RX_DATA_DECODING {64B66B} \
+                         CONFIG.RX_REFCLK_SOURCE {X0Y7 clk1 X0Y6 clk1 X0Y5 clk1 X0Y4 clk1 X0Y3 clk1 X0Y2 clk1 X0Y1 clk1 X0Y0 clk1} \
+                         CONFIG.TX_REFCLK_SOURCE {X0Y7 clk1 X0Y6 clk1 X0Y5 clk1 X0Y4 clk1 X0Y3 clk1 X0Y2 clk1 X0Y1 clk1 X0Y0 clk1} \
+                         CONFIG.LOCATE_IN_SYSTEM_IBERT_CORE {EXAMPLE_DESIGN} \
+                         CONFIG.TX_USER_DATA_WIDTH {64} \
+                         CONFIG.TX_INT_DATA_WIDTH {64} \
+                         CONFIG.RX_USER_DATA_WIDTH {64} \
+                         CONFIG.RX_INT_DATA_WIDTH {64} \
+                         CONFIG.RX_JTOL_FC {10} \
+                         CONFIG.RX_CB_MAX_LEVEL {4} \
+                         CONFIG.TXPROGDIV_FREQ_SOURCE {QPLL1} \
+                         CONFIG.TXPROGDIV_FREQ_VAL {312.5} \
+                         CONFIG.ENABLE_OPTIONAL_PORTS {rxpolarity_in}] [get_ips DLx_phy]
+generate_target {all} [get_ips DLx_phy]

board_support_packages/ad9v3/verilog/xilinx/encrypted_elastic_buffer/DLx_phy_example_bit_sync.v

@@ -0,0 +1,88 @@
+`pragma protect begin_protected
+`pragma protect version = 2
+`pragma protect encrypt_agent = "XILINX"
+`pragma protect encrypt_agent_info = "Xilinx Encryption Tool 2015"
+`pragma protect begin_commonblock
+`pragma protect end_commonblock
+`pragma protect begin_toolblock
+`pragma protect rights_digest_method="sha256"
+`pragma protect key_keyowner = "Xilinx", key_keyname= "xilinxt_2017_05", key_method = "rsa", key_block
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+
+`pragma protect end_toolblock="+FRfzE+YyH+0kw/c/Wfdo6btp9UtVrhHV7UYRKzSoOw="
+`pragma protect data_method = "AES128-CBC"
+`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 3824)
+`pragma protect data_block
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+`pragma protect end_protected