Addition of Burst Mode for SPI byte transactions

Author: fcandelario

src/SpiController.vhd

@@ -6,12 +6,14 @@
 --  Contributor(s):
 --     Guy Eschemann   (original Author of SPI.vhd)
 --     Jacob Albers
+--     fernandoka
 --
 --  Description:
 --      SPI Controller Verification Component
 --
 --  Revision History:
 --    Date      Version    Description
+--    11/2024   2024.03    Addition of Burst Mode for SPI byte transactions
 --    03/2024   2024.03    Updated SafeResize to use ModelID
 --    06/2022   2022.06    Initial version
 --
@@ -92,6 +94,7 @@ architecture model of SpiController is
     signal OptSpiMode           : SpiModeType          := SPI_MODE;
     signal CPOL                 : std_logic            := '0';
     signal CPHA                 : std_logic            := '0';
+    signal SpiBurstModeEna      : boolean              :=  false;
     -- SPI Clock Signals
     signal SpiClk               : std_logic            := '0';
     signal OptSclkPeriod        : SpiClkType           :=  SCLK_PERIOD;
@@ -209,6 +212,13 @@ begin
                             to_string(TransRec.IntToModel),
                             INFO);
 
+                        when SpiOptionType'pos(SET_SPI_BURST_MODE) =>
+                        SpiBurstModeEna <= TransRec.BoolToModel;
+                        -- Log SPI mode change
+                        Log(ModelID, "Set SPI Burst Mode = " &
+                            to_string(TransRec.BoolToModel),
+                            INFO);
+
                         when others =>
                             Alert(ModelID, OPT_ERR_MSG &
                                   to_string(SpiOptionType'val(TransRec.Options)),
@@ -235,6 +245,7 @@ begin
 
     SpiTxHandler : process
         variable TxData      : std_logic_vector(7 downto 0);
+        variable BurstEna    : boolean := false;
 
     begin
         wait for 0 ns;
@@ -259,10 +270,13 @@ begin
 
             -- SPI Mode: Propogate any SPI Mode changes
             SetSpiParams(OptSpiMode, CPOL, CPHA);
+            BurstEna := SpiBurstModeEna;
 
             -- SCLK: Wait for correct SpiClk phase before engaging CSEL
-            wait until SpiClk = CPOL and SpiClk'event;
-            CSEL <= '0';
+            if CSEL='1' then
+              wait until SpiClk = CPOL and SpiClk'event;
+              CSEL <= '0';
+            end if;
 
             -- Transmit TxData byte bit by bit
             for BitIdx in 7 downto 0 loop
@@ -275,12 +289,19 @@ begin
                 end if;
 
                 PICO <= TxData(BitIdx) when OptSpiMode = 1 or OptSpiMode = 3;
+
+                Log(ModelID, "Loop: SPI Controller TxData: " & to_string(TxData) &
+                    ", PICO # " & to_string(TxData(BitIdx)) &
+                    ", BitIdx # " & to_string(BitIdx),
+                    DEBUG);
             end loop;
 
-            wait until SpiClk /= CPOL and SpiClk'event;
             Increment(TransmitDoneCount);
-            CSEL <= '1';
-            PICO <= '0';
+            if not BurstEna or ((TransmitDoneCount+1)=TransmitRequestCount) then
+              wait until SpiClk /= CPOL and SpiClk'event;
+              CSEL <= '1';
+              PICO <= '0';
+            end if;
 
         end loop ControllerTxLoop;
     end process SpiTxHandler;

src/SpiPeripheral.vhd

@@ -6,12 +6,14 @@
 --  Contributor(s):
 --     Guy Eschemann   (original Author of SPI.vhd)
 --     Jacob Albers
+--     fernandoka
 --
 --  Description:
 --      SPI Peripheral Verification Component
 --
 --  Revision History:
 --    Date      Version    Description
+--    11/2024   2024.03    Addition of Burst Mode for SPI byte transactions
 --    04/2024   2024.04    Initial version
 --
 --  This file is part of OSVVM.
@@ -220,15 +222,19 @@ begin
     -- SPI Peripheral Receive Functionality
     ----------------------------------------------------------------------------
     SpiRxHandler : process
-        variable RxData : std_logic_vector(7 downto 0) := (others => '0');
-        variable BitCnt : integer;
+        variable RxData  : std_logic_vector(7 downto 0) := (others => '0');
+        variable BitCnt  : integer;
+        variable CsIsLow : boolean := false;
 
     begin
         wait for 0 ns;
 
         PeripheralRxLoop : loop
             BitCnt := 0;
-            wait until falling_edge(CSEL);
+            if not CsIsLow then
+              wait until falling_edge(CSEL);
+              CsIsLow := true;
+            end if;
 
             -- SPI Mode: Propogate SPI Mode changes
             SetSpiParams(OptSpiMode, CPOL, CPHA);
@@ -237,18 +243,23 @@ begin
             -- Clock in bits while CSEL low
             while CSEL = '0' and BitCnt <= RxData'length - 1 loop
                 if OptSpiMode = 0 or OptSpiMode = 3 then
-                    wait until rising_edge(SCLK);
+                    wait until rising_edge(SCLK) or rising_edge(CSEL);
                 else
-                    wait until falling_edge(SCLK);
+                    wait until falling_edge(SCLK) or rising_edge(CSEL);
                 end if;
 
-                RxData := RxData(RxData'high - 1 downto RxData'low) &
-                PICO;
-                BitCnt := BitCnt + 1; -- Counter feels lazy but *shrug*
+                CsIsLow := CSEL='0'; -- Update CsIsLow
+                if CsIsLow then
+                  RxData := RxData(RxData'high - 1 downto RxData'low) &
+                  PICO;
+                  BitCnt := BitCnt + 1; -- Counter feels lazy but *shrug*
+                end if;
             end loop;
 
+          if BitCnt=RxData'length then
             Push(ReceiveFifo, RxData);
             Increment(ReceiveCount);
+          end if;
         end loop PeripheralRxLoop;
 
     end process SpiRxHandler;
@@ -257,17 +268,24 @@ begin
     -- SPI Peripheral Transmit Functionality
     ----------------------------------------------------------------------------
     SpiTxHandler : process
-        variable TxData : std_logic_vector(7 downto 0);
-        variable BitIdx : integer;
-
+        variable TxData            : std_logic_vector(7 downto 0);
+        variable BitIdx            : integer;
+        variable CsIsLow           : boolean := false;
+        variable TransmitIsPending : boolean := false;
     begin
         wait for 0 ns;
 
         PeripheralTxLoop : loop
-            wait until CSEL = '0';
-            if not Empty(TransmitFifo) then
+            if not CsIsLow then
+              wait until falling_edge(CSEL);
+              CsIsLow := true;
+            end if;
+
+
+            if not Empty(TransmitFifo) and not TransmitIsPending then
                 TxData := Pop(TransmitFifo);
-            else
+                TransmitIsPending := true;
+            elsif not TransmitIsPending then
                 TxData := (others => '0');
             end if;
 
@@ -277,14 +295,23 @@ begin
                 POCI <= TxData(BitIdx) when OptSpiMode = 0 or OptSpiMode = 2;
 
                 if OptSpiMode = 0 or OptSpiMode = 3 then
-                    wait until falling_edge(SCLK);
+                    wait until falling_edge(SCLK) or rising_edge(CSEL);
                 else
-                    wait until rising_edge(SCLK);
+                    wait until rising_edge(SCLK) or rising_edge(CSEL);
                 end if;
 
-                POCI <= TxData(BitIdx) when OptSpiMode = 1 or OptSpiMode = 3;
-                BitIdx := BitIdx - 1;
+                CsIsLow := CSEL='0'; -- Update CsIsLow
+                if CsIsLow then
+                  POCI <= TxData(BitIdx) when OptSpiMode = 1 or OptSpiMode = 3;
+                  BitIdx := BitIdx - 1;
+                end if;
             end loop;
+
+            if BitIdx<0 then
+              Increment(TransmitDoneCount);
+              TransmitIsPending := false;
+            end if;
+
         end loop PeripheralTxLoop;
     end process SpiTxHandler;
 end architecture model;

src/SpiTbPkg.vhd

@@ -6,12 +6,14 @@
 --  Contributor(s):
 --     Guy Eschemann   (original Author)
 --     Jacob Albers
+--     fernandoka
 --
 --  Description:
 --      Constant and Transaction Support for OSVVM SPI VC
 --
 --  Revision History:
 --    Date      Version    Description
+--    11/2024   2024.03    Addition of Burst Mode for SPI byte transactions
 --    04/2024   2024.04    Initial version
 --    06/2022   2022.06    Initial version
 --
@@ -79,7 +81,8 @@ package SpiTbPkg is
     ----------------------------------------------------------------------------
     type SpiOptionType is (
         SET_SCLK_PERIOD,
-        SET_SPI_MODE
+        SET_SPI_MODE,
+        SET_SPI_BURST_MODE
     );
 
     ----------------------------------------------------------------------------
@@ -116,6 +119,11 @@ package SpiTbPkg is
         signal CPHA           : out std_logic
     );
 
+    procedure SetSpiBurstMode(
+        signal   TransactionRec  : inout StreamRecType;
+        constant SpiBurstModeEna : boolean
+    );
+
     ----------------------------------------------------------------------------
     -- SPI Parameter Helpers
     ----------------------------------------------------------------------------
@@ -164,6 +172,19 @@ package body SpiTbPkg is
         CPHA      <= GetCPHA(OptSpiMode);
     end procedure SetSpiParams;
 
+    ----------------------------------------------------------------------------
+    -- SetSpiBurstMode: Sets SPI device byte transaction characteristics
+    ----------------------------------------------------------------------------
+    procedure SetSpiBurstMode(
+        signal   TransactionRec  : inout StreamRecType;
+        constant SpiBurstModeEna : boolean
+    ) is
+    begin
+        SetModelOptions(TransactionRec,
+                        SpiOptionType'pos(SET_SPI_BURST_MODE),
+                        SpiBurstModeEna);
+    end procedure SetSpiBurstMode;
+
     ----------------------------------------------------------------------------
     -- GetCPOL: Helper function for SetSpiMode returns CPOL value
     ----------------------------------------------------------------------------

testbench/TbSpi.vhd

@@ -81,15 +81,15 @@ begin
     ------------------------------------------------------------
     -- Create Clock
     ------------------------------------------------------------
-    Osvvm.ClockResetPkg.CreateClock(
+    Osvvm.TbUtilPkg.CreateClock(
         Clk    => Clk,
         Period => tperiod_Clk
     );
 
     ------------------------------------------------------------
     -- Create Reset
     ------------------------------------------------------------
-    Osvvm.ClockResetPkg.CreateReset(
+    Osvvm.TbUtilPkg.CreateReset(
         Reset       => n_Reset,
         ResetActive => '0',
         Clk         => Clk,