1+ --
2+ -- File Name: TbStream_SendCheckBurstVector1.vhd
3+ -- Design Unit Name: Architecture of TestCtrl
4+ -- Revision: OSVVM MODELS STANDARD VERSION
5+ --
6+ -- Maintainer: Jim Lewis email: [email protected] 7+ -- Contributor(s):
8+ 9+ --
10+ --
11+ -- Description:
12+ -- Burst Transactions with Full Data Width
13+ -- SendBurst, GetBurst
14+ --
15+ --
16+ -- Developed by:
17+ -- SynthWorks Design Inc.
18+ -- VHDL Training Classes
19+ -- http://www.SynthWorks.com
20+ --
21+ -- Revision History:
22+ -- Date Version Description
23+ -- 10/2020 2020.10 Initial revision
24+ --
25+ --
26+ -- This file is part of OSVVM.
27+ --
28+ -- Copyright (c) 2018 - 2020 by SynthWorks Design Inc.
29+ --
30+ -- Licensed under the Apache License, Version 2.0 (the "License");
31+ -- you may not use this file except in compliance with the License.
32+ -- You may obtain a copy of the License at
33+ --
34+ -- https://www.apache.org/licenses/LICENSE-2.0
35+ --
36+ -- Unless required by applicable law or agreed to in writing, software
37+ -- distributed under the License is distributed on an "AS IS" BASIS,
38+ -- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
39+ -- See the License for the specific language governing permissions and
40+ -- limitations under the License.
41+ --
42+ architecture SendCheckBurstVector1 of TestCtrl is
43+
44+ signal TestDone : integer_barrier := 1 ;
45+ -- constant FIFO_WIDTH : integer := DATA_WIDTH ;
46+ constant FIFO_WIDTH : integer := 8 ; -- BYTE
47+
48+ signal SB : ScoreboardIDType ;
49+
50+ begin
51+
52+ -- ----------------------------------------------------------
53+ -- ControlProc
54+ -- Set up AlertLog and wait for end of test
55+ -- ----------------------------------------------------------
56+ ControlProc : process
57+ begin
58+ -- Initialization of test
59+ SetTestName(" TbStream_SendCheckBurstVector1"
60+ SetLogEnable(PASSED, TRUE ) ; -- Enable PASSED logs
61+ SetLogEnable(INFO, TRUE ) ; -- Enable INFO logs
62+
63+ -- Wait for testbench initialization
64+ wait for 0 ns ; wait for 0 ns ;
65+ TranscriptOpen ;
66+ SetTranscriptMirror(TRUE ) ;
67+ SB <= NewID(" SB"
68+
69+ -- Wait for Design Reset
70+ wait until nReset = '1' ;
71+ ClearAlerts ;
72+
73+ -- Wait for test to finish
74+ WaitForBarrier(TestDone, 5 ms ) ;
75+ AlertIf(now >= 5 ms , " Test finished due to timeout"
76+ AlertIf(GetAffirmCount < 1 , " Test is not Self-Checking"
77+
78+ TranscriptClose ;
79+ -- AlertIfDiff("./results/TbStream_SendCheckBurstVector1.txt", "../sim_shared/validated_results/TbStream_SendCheckBurstVector1.txt", "") ;
80+
81+ EndOfTestReports ;
82+ std.env.stop ;
83+ wait ;
84+ end process ControlProc ;
85+
86+
87+ -- ----------------------------------------------------------
88+ -- AxiTransmitterProc
89+ -- Generate transactions for AxiTransmitter
90+ -- ----------------------------------------------------------
91+ AxiTransmitterProc : process
92+ variable ByteData : integer_vector(1 to 16 ) ;
93+ variable RV : RandomPType ;
94+ variable ID : std_logic_vector (ID_LEN- 1 downto 0 ) ; -- 8
95+ variable Dest : std_logic_vector (DEST_LEN- 1 downto 0 ) ; -- 4
96+ variable User : std_logic_vector (USER_LEN- 1 downto 0 ) ; -- 4
97+ variable Param : std_logic_vector (ID_LEN + DEST_LEN + USER_LEN downto 0 ) ;
98+ begin
99+ ID := to_slv(1 , ID_LEN);
100+ Dest := to_slv(2 , DEST_LEN) ;
101+ User := to_slv(3 , USER_LEN) ;
102+ Param := ID & Dest & User & '1' ;
103+
104+ RV.InitSeed(RV'path_name) ;
105+ wait until nReset = '1' ;
106+ WaitForClock(StreamTxRec, 2 ) ;
107+ SetBurstMode(StreamTxRec, STREAM_BURST_BYTE_MODE) ;
108+
109+ SendBurstVector(StreamTxRec, (1 ,3 ,5 ,7 ,9 ,11 ,13 ,15 ,17 ,19 ,21 ,23 ,25 ,27 ,29 ), FIFO_WIDTH) ;
110+ SendBurstVector(StreamTxRec, (31 ,33 ,35 ,37 ,39 ,41 ,43 ,45 ,47 ,49 ,51 ,53 ), Param, FIFO_WIDTH) ;
111+ SendBurstVector(StreamTxRec, (2 ,4 ,6 ,8 ,10 ,12 ,14 ,16 ,18 ,20 ), FIFO_WIDTH) ;
112+
113+ WaitForClock(StreamTxRec, 4 ) ;
114+
115+ ByteData(1 to 14 ) := RV.RandIntV(0 ,255 ,14 ) ;
116+ PushBurstVector(SB, ByteData(1 to 14 ), FIFO_WIDTH) ;
117+ SendBurstVector(StreamTxRec, ByteData(1 to 14 ), FIFO_WIDTH) ;
118+
119+
120+ -- Wait for outputs to propagate and signal TestDone
121+ WaitForClock(StreamTxRec, 2 ) ;
122+ WaitForBarrier(TestDone) ;
123+ wait ;
124+ end process AxiTransmitterProc ;
125+
126+
127+ -- ----------------------------------------------------------
128+ -- AxiReceiverProc
129+ -- Generate transactions for AxiReceiver
130+ -- ----------------------------------------------------------
131+ AxiReceiverProc : process
132+ variable BurstLen : integer ;
133+ variable ID : std_logic_vector (ID_LEN- 1 downto 0 ) ; -- 8
134+ variable Dest : std_logic_vector (DEST_LEN- 1 downto 0 ) ; -- 4
135+ variable User : std_logic_vector (USER_LEN- 1 downto 0 ) ; -- 4
136+ variable Param : std_logic_vector (ID_LEN + DEST_LEN + USER_LEN downto 0 ) ;
137+ begin
138+ ID := to_slv(1 , ID_LEN);
139+ Dest := to_slv(2 , DEST_LEN) ;
140+ User := to_slv(3 , USER_LEN) ;
141+ Param := ID & Dest & User & '1' ;
142+ WaitForClock(StreamRxRec, 2 ) ;
143+ SetBurstMode(StreamRxRec, STREAM_BURST_BYTE_MODE) ;
144+
145+ -- log("Transmit 30 Bytes -- unaligned") ;
146+ CheckBurstVector(StreamRxRec, (1 ,3 ,5 ,7 ,9 ,11 ,13 ,15 ,17 ,19 ,21 ,23 ,25 ,27 ,29 ), FIFO_WIDTH) ;
147+ CheckBurstVector(StreamRxRec, (31 ,33 ,35 ,37 ,39 ,41 ,43 ,45 ,47 ,49 ,51 ,53 ), Param, FIFO_WIDTH) ;
148+ CheckBurstVector(StreamRxRec, (2 ,4 ,6 ,8 ,10 ,12 ,14 ,16 ,18 ,20 ), FIFO_WIDTH) ;
149+
150+ WaitForClock(StreamRxRec, 4 ) ;
151+
152+ GetBurst(StreamRxRec, BurstLen) ;
153+ CheckBurstFifo(SB, StreamRxRec.BurstFifo, BurstLen) ;
154+
155+ -- Wait for outputs to propagate and signal TestDone
156+ WaitForClock(StreamRxRec, 2 ) ;
157+ WaitForBarrier(TestDone) ;
158+ wait ;
159+ end process AxiReceiverProc ;
160+
161+ end SendCheckBurstVector1 ;
162+
163+ Configuration TbStream_SendCheckBurstVector1 of TbStream is
164+ for TestHarness
165+ for TestCtrl_1 : TestCtrl
166+ use entity work.TestCtrl(SendCheckBurstVector1) ;
167+ end for ;
168+ end for ;
169+ end TbStream_SendCheckBurstVector1 ;
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