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DE1_SoC_TV.map.rpt
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Analysis & Synthesis report for DE1_SoC_TV
Tue Dec 01 19:13:15 2015
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Parallel Compilation
5. Analysis & Synthesis Source Files Read
6. Analysis & Synthesis Resource Usage Summary
7. Analysis & Synthesis Resource Utilization by Entity
8. Analysis & Synthesis RAM Summary
9. Analysis & Synthesis DSP Block Usage Summary
10. Analysis & Synthesis IP Cores Summary
11. State Machine - |DE1_SoC_TV|I2C_AV_Config:u1|mSetup_ST
12. State Machine - |DE1_SoC_TV|Shooter:gameLogic|currentState
13. Registers Removed During Synthesis
14. Removed Registers Triggering Further Register Optimizations
15. General Register Statistics
16. Inverted Register Statistics
17. Multiplexer Restructuring Statistics (Restructuring Performed)
18. Source assignments for DIV:u5|lpm_divide:LPM_DIVIDE_component|lpm_divide_h3t:auto_generated|sign_div_unsign_3li:divider|alt_u_div_tuf:divider
19. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component
20. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated
21. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_nv6:rdptr_g1p
22. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p
23. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram
24. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_brp
25. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_bwp
26. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp
27. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe13
28. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_brp
29. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_bwp
30. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp
31. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16
32. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component
33. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated
34. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_nv6:rdptr_g1p
35. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p
36. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram
37. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_brp
38. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_bwp
39. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp
40. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe13
41. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_brp
42. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_bwp
43. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp
44. Source assignments for Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16
45. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component
46. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated
47. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_nv6:rdptr_g1p
48. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p
49. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram
50. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_brp
51. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_bwp
52. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp
53. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe13
54. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_brp
55. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_bwp
56. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp
57. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16
58. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component
59. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated
60. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_nv6:rdptr_g1p
61. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p
62. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram
63. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_brp
64. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_bwp
65. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp
66. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe13
67. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_brp
68. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_bwp
69. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp
70. Source assignments for Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16
71. Source assignments for multiFrameStorage:frame1|frameStorage:FS1|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated
72. Source assignments for multiFrameStorage:frame1|frameStorage:FS2|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated
73. Source assignments for multiFrameStorage:frame1|frameStorage:FS3|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated
74. Source assignments for multiFrameStorage:frame1|frameStorage:FS4|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated
75. Source assignments for multiFrameStorage:frame1|frameStorage:FS5|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated
76. Source assignments for multiFrameStorage:frame1|frameStorage:FS6|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated
77. Source assignments for multiFrameStorage:frame1|frameStorage:FS7|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated
78. Source assignments for multiFrameStorage:frame1|frameStorage:FS8|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated
79. Source assignments for multiFrameStorage:frame1|frameStorage:FS9|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated
80. Source assignments for multiFrameStorage:frame1|frameStorage:FS10|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated
81. Source assignments for Background2:background|altsyncram:altsyncram_component|altsyncram_b6g1:auto_generated
82. Source assignments for TScreen:title|altsyncram:altsyncram_component|altsyncram_akg1:auto_generated
83. Source assignments for Reticle:reticle|altsyncram:altsyncram_component|altsyncram_4bg1:auto_generated
84. Source assignments for Line_Buffer:u10|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|altsyncram_ffj1:altsyncram2
85. Source assignments for Line_Buffer:u10|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|cntr_b6h:cntr3
86. Source assignments for Line_Buffer:u11|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|altsyncram_ffj1:altsyncram2
87. Source assignments for Line_Buffer:u11|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|cntr_b6h:cntr3
88. Parameter Settings for User Entity Instance: Top-level Entity: |DE1_SoC_TV
89. Parameter Settings for User Entity Instance: DIV:u5|lpm_divide:LPM_DIVIDE_component
90. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6
91. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|Sdram_PLL_0002:sdram_pll_inst|altera_pll:altera_pll_i
92. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|control_interface:control1
93. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|command:command1
94. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|sdr_data_path:data_path1
95. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component
96. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component
97. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component
98. Parameter Settings for User Entity Instance: Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component
99. Parameter Settings for User Entity Instance: Cursor:Cursor1
100. Parameter Settings for User Entity Instance: Shooter:gameLogic
101. Parameter Settings for User Entity Instance: Shooter:gameLogic|Target:T1
102. Parameter Settings for User Entity Instance: Shooter:gameLogic|Target:T2
103. Parameter Settings for User Entity Instance: Shooter:gameLogic|Target:T3
104. Parameter Settings for User Entity Instance: Shooter:gameLogic|Target:T4
105. Parameter Settings for User Entity Instance: Shooter:gameLogic|Target:T5
106. Parameter Settings for User Entity Instance: Shooter:gameLogic|Target:T6
107. Parameter Settings for User Entity Instance: Shooter:gameLogic|Target:T7
108. Parameter Settings for User Entity Instance: Shooter:gameLogic|Target:T8
109. Parameter Settings for User Entity Instance: Shooter:gameLogic|Target:T9
110. Parameter Settings for User Entity Instance: Shooter:gameLogic|Target:T10
111. Parameter Settings for User Entity Instance: TimeDisplayController:timeController
112. Parameter Settings for User Entity Instance: multiFrameStorage:frame1
113. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS1
114. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS1|altsyncram:altsyncram_component
115. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS2
116. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS2|altsyncram:altsyncram_component
117. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS3
118. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS3|altsyncram:altsyncram_component
119. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS4
120. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS4|altsyncram:altsyncram_component
121. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS5
122. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS5|altsyncram:altsyncram_component
123. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS6
124. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS6|altsyncram:altsyncram_component
125. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS7
126. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS7|altsyncram:altsyncram_component
127. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS8
128. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS8|altsyncram:altsyncram_component
129. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS9
130. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS9|altsyncram:altsyncram_component
131. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS10
132. Parameter Settings for User Entity Instance: multiFrameStorage:frame1|frameStorage:FS10|altsyncram:altsyncram_component
133. Parameter Settings for User Entity Instance: Background2:background|altsyncram:altsyncram_component
134. Parameter Settings for User Entity Instance: TScreen:title|altsyncram:altsyncram_component
135. Parameter Settings for User Entity Instance: Reticle:reticle|altsyncram:altsyncram_component
136. Parameter Settings for User Entity Instance: VGA_Ctrl:u9
137. Parameter Settings for User Entity Instance: Line_Buffer:u10|altshift_taps:ALTSHIFT_TAPS_component
138. Parameter Settings for User Entity Instance: Line_Buffer:u11|altshift_taps:ALTSHIFT_TAPS_component
139. Parameter Settings for User Entity Instance: AUDIO_DAC:u12
140. Parameter Settings for User Entity Instance: I2C_AV_Config:u1
141. Parameter Settings for Inferred Entity Instance: TimeDisplayController:timeController|lpm_divide:Mod2
142. Parameter Settings for Inferred Entity Instance: TimeDisplayController:timeController|lpm_divide:Mod3
143. Parameter Settings for Inferred Entity Instance: TimeDisplayController:timeController|lpm_divide:Div0
144. Parameter Settings for Inferred Entity Instance: TimeDisplayController:timeController|lpm_divide:Div1
145. Parameter Settings for Inferred Entity Instance: TimeDisplayController:timeController|lpm_divide:Mod1
146. Parameter Settings for Inferred Entity Instance: TimeDisplayController:timeController|lpm_divide:Mod0
147. Parameter Settings for Inferred Entity Instance: TimeDisplayController:timeController|lpm_divide:Div2
148. Parameter Settings for Inferred Entity Instance: TimeDisplayController:timeController|lpm_divide:Mod4
149. Parameter Settings for Inferred Entity Instance: lpm_divide:Div7
150. Parameter Settings for Inferred Entity Instance: lpm_divide:Div38
151. Parameter Settings for Inferred Entity Instance: lpm_divide:Div39
152. Parameter Settings for Inferred Entity Instance: lpm_divide:Div31
153. Parameter Settings for Inferred Entity Instance: lpm_divide:Div15
154. Parameter Settings for Inferred Entity Instance: lpm_divide:Div23
155. Parameter Settings for Inferred Entity Instance: Cursor:Cursor1|ImageProcessor:imProcR|lpm_divide:Div1
156. Parameter Settings for Inferred Entity Instance: Cursor:Cursor1|ImageProcessor:imProcR|lpm_divide:Div0
157. Parameter Settings for Inferred Entity Instance: Shooter:gameLogic|Target:T1|lpm_divide:Mod0
158. Parameter Settings for Inferred Entity Instance: Shooter:gameLogic|Target:T2|lpm_divide:Mod0
159. Parameter Settings for Inferred Entity Instance: Shooter:gameLogic|Target:T5|lpm_divide:Mod0
160. Parameter Settings for Inferred Entity Instance: Shooter:gameLogic|Target:T6|lpm_divide:Mod0
161. Parameter Settings for Inferred Entity Instance: Shooter:gameLogic|Target:T7|lpm_divide:Mod0
162. Parameter Settings for Inferred Entity Instance: Shooter:gameLogic|Target:T8|lpm_divide:Mod0
163. Parameter Settings for Inferred Entity Instance: Shooter:gameLogic|Target:T9|lpm_divide:Mod0
164. Parameter Settings for Inferred Entity Instance: Shooter:gameLogic|Target:T10|lpm_divide:Mod0
165. Parameter Settings for Inferred Entity Instance: Shooter:gameLogic|Target:T3|lpm_divide:Mod0
166. Parameter Settings for Inferred Entity Instance: Shooter:gameLogic|Target:T4|lpm_divide:Mod0
167. Parameter Settings for Inferred Entity Instance: Cursor:Cursor1|ImageProcessor:imProcG|lpm_divide:Div0
168. Parameter Settings for Inferred Entity Instance: Cursor:Cursor1|ImageProcessor:imProcG|lpm_divide:Div1
169. dcfifo Parameter Settings by Entity Instance
170. altsyncram Parameter Settings by Entity Instance
171. altshift_taps Parameter Settings by Entity Instance
172. Port Connectivity Checks: "I2C_AV_Config:u1|I2C_Controller:u0"
173. Port Connectivity Checks: "AUDIO_DAC:u12"
174. Port Connectivity Checks: "Line_Buffer:u11"
175. Port Connectivity Checks: "Line_Buffer:u10"
176. Port Connectivity Checks: "VGA_Ctrl:u9"
177. Port Connectivity Checks: "TScreen:title"
178. Port Connectivity Checks: "multiFrameStorage:frame1|frameStorage:FS10"
179. Port Connectivity Checks: "multiFrameStorage:frame1|frameStorage:FS9"
180. Port Connectivity Checks: "multiFrameStorage:frame1|frameStorage:FS8"
181. Port Connectivity Checks: "multiFrameStorage:frame1|frameStorage:FS7"
182. Port Connectivity Checks: "multiFrameStorage:frame1|frameStorage:FS6"
183. Port Connectivity Checks: "multiFrameStorage:frame1|frameStorage:FS5"
184. Port Connectivity Checks: "multiFrameStorage:frame1|frameStorage:FS4"
185. Port Connectivity Checks: "multiFrameStorage:frame1|frameStorage:FS3"
186. Port Connectivity Checks: "multiFrameStorage:frame1|frameStorage:FS2"
187. Port Connectivity Checks: "multiFrameStorage:frame1|frameStorage:FS1"
188. Port Connectivity Checks: "Shooter:gameLogic|Target:T10|LFSR:randomGenerator2"
189. Port Connectivity Checks: "Shooter:gameLogic|Target:T10|LFSR:randomGenerator1"
190. Port Connectivity Checks: "Shooter:gameLogic|Target:T10"
191. Port Connectivity Checks: "Shooter:gameLogic|Target:T9|LFSR:randomGenerator2"
192. Port Connectivity Checks: "Shooter:gameLogic|Target:T9|LFSR:randomGenerator1"
193. Port Connectivity Checks: "Shooter:gameLogic|Target:T9"
194. Port Connectivity Checks: "Shooter:gameLogic|Target:T8|LFSR:randomGenerator2"
195. Port Connectivity Checks: "Shooter:gameLogic|Target:T8|LFSR:randomGenerator1"
196. Port Connectivity Checks: "Shooter:gameLogic|Target:T8"
197. Port Connectivity Checks: "Shooter:gameLogic|Target:T7|LFSR:randomGenerator2"
198. Port Connectivity Checks: "Shooter:gameLogic|Target:T7|LFSR:randomGenerator1"
199. Port Connectivity Checks: "Shooter:gameLogic|Target:T7"
200. Port Connectivity Checks: "Shooter:gameLogic|Target:T6|LFSR:randomGenerator2"
201. Port Connectivity Checks: "Shooter:gameLogic|Target:T6|LFSR:randomGenerator1"
202. Port Connectivity Checks: "Shooter:gameLogic|Target:T6"
203. Port Connectivity Checks: "Shooter:gameLogic|Target:T5|LFSR:randomGenerator2"
204. Port Connectivity Checks: "Shooter:gameLogic|Target:T5|LFSR:randomGenerator1"
205. Port Connectivity Checks: "Shooter:gameLogic|Target:T5"
206. Port Connectivity Checks: "Shooter:gameLogic|Target:T4|LFSR:randomGenerator2"
207. Port Connectivity Checks: "Shooter:gameLogic|Target:T4|LFSR:randomGenerator1"
208. Port Connectivity Checks: "Shooter:gameLogic|Target:T4"
209. Port Connectivity Checks: "Shooter:gameLogic|Target:T3|LFSR:randomGenerator2"
210. Port Connectivity Checks: "Shooter:gameLogic|Target:T3|LFSR:randomGenerator1"
211. Port Connectivity Checks: "Shooter:gameLogic|Target:T3"
212. Port Connectivity Checks: "Shooter:gameLogic|Target:T2|LFSR:randomGenerator2"
213. Port Connectivity Checks: "Shooter:gameLogic|Target:T2|LFSR:randomGenerator1"
214. Port Connectivity Checks: "Shooter:gameLogic|Target:T2"
215. Port Connectivity Checks: "Shooter:gameLogic|Target:T1|LFSR:randomGenerator2"
216. Port Connectivity Checks: "Shooter:gameLogic|Target:T1|LFSR:randomGenerator1"
217. Port Connectivity Checks: "Shooter:gameLogic|Target:T1"
218. Port Connectivity Checks: "Shooter:gameLogic"
219. Port Connectivity Checks: "Cursor:Cursor1|ImageProcessor:imProcG"
220. Port Connectivity Checks: "Cursor:Cursor1|ImageProcessor:imProcR"
221. Port Connectivity Checks: "Cursor:Cursor1"
222. Port Connectivity Checks: "YUV422_to_444:u7"
223. Port Connectivity Checks: "Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2"
224. Port Connectivity Checks: "Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1"
225. Port Connectivity Checks: "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2"
226. Port Connectivity Checks: "Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1"
227. Port Connectivity Checks: "Sdram_Control_4Port:u6|sdr_data_path:data_path1"
228. Port Connectivity Checks: "Sdram_Control_4Port:u6|control_interface:control1"
229. Port Connectivity Checks: "Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1"
230. Port Connectivity Checks: "Sdram_Control_4Port:u6"
231. Port Connectivity Checks: "DIV:u5"
232. Port Connectivity Checks: "ITU_656_Decoder:u4"
233. Port Connectivity Checks: "TD_Detect:u2"
234. Elapsed Time Per Partition
235. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-------------------------------------+-------------------------------------------------+
; Analysis & Synthesis Status ; Successful - Tue Dec 01 19:13:15 2015 ;
; Quartus II 64-Bit Version ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
; Revision Name ; DE1_SoC_TV ;
; Top-level Entity Name ; DE1_SoC_TV ;
; Family ; Cyclone V ;
; Logic utilization (in ALMs) ; N/A ;
; Total registers ; 2707 ;
; Total pins ; 168 ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 2,428,280 ;
; Total DSP Blocks ; 19 ;
; Total HSSI RX PCSs ; 0 ;
; Total HSSI PMA RX Deserializers ; 0 ;
; Total HSSI PMA RX ATT Deserializers ; 0 ;
; Total HSSI TX PCSs ; 0 ;
; Total HSSI PMA TX Serializers ; 0 ;
; Total HSSI PMA TX ATT Serializers ; 0 ;
; Total PLLs ; 1 ;
; Total DLLs ; 0 ;
+-------------------------------------+-------------------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
; Device ; 5CSEMA5F31C6 ; ;
; Top-level entity name ; DE1_SoC_TV ; DE1_SoC_TV ;
; Family name ; Cyclone V ; Cyclone IV GX ;
; Optimization Technique ; Speed ; Balanced ;
; Use smart compilation ; Off ; Off ;
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
; Enable compact report table ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Infer RAMs from Raw Logic ; On ; On ;
; Parallel Synthesis ; On ; On ;
; DSP Block Balancing ; Auto ; Auto ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Carry Chain Length ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto DSP Block Replacement ; On ; On ;
; Auto Shift Register Replacement ; Auto ; Auto ;
; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Allow Synchronous Control Signals ; On ; On ;
; Force Use of Synchronous Clear Signals ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Allow Any Shift Register Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Timing-Driven Synthesis ; On ; On ;
; Report Parameter Settings ; On ; On ;
; Report Source Assignments ; On ; On ;
; Report Connectivity Checks ; On ; On ;
; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
; Synchronization Register Chain Length ; 3 ; 3 ;
; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Clock MUX Protection ; On ; On ;
; Auto Gated Clock Conversion ; Off ; Off ;
; Block Design Naming ; Auto ; Auto ;
; SDC constraint protection ; Off ; Off ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
; Resource Aware Inference For Block RAM ; On ; On ;
; Synthesis Seed ; 1 ; 1 ;
; Automatic Parallel Synthesis ; Off ; Off ;
+---------------------------------------------------------------------------------+--------------------+--------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 8 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+------------------------------------------------+-----------------+----------------------------------------+-------------------------------------------------------------------------------+-----------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
+------------------------------------------------+-----------------+----------------------------------------+-------------------------------------------------------------------------------+-----------+
; TScreen.v ; yes ; User Wizard-Generated File ; D:/School/ECE 241/Project0.85/TScreen.v ; ;
; Background2.v ; yes ; User Wizard-Generated File ; D:/School/ECE 241/Project0.85/Background2.v ; ;
; ram files/Reticle.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/ram files/Reticle.v ; ;
; TimeDisplay.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/TimeDisplay.v ; ;
; Shooter.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/Shooter.v ; ;
; ram files/frameStorage.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/ram files/frameStorage.v ; ;
; Cursor.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/Cursor.v ; ;
; DE1_SoC_TV.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/DE1_SoC_TV.v ; ;
; ImageProcessor.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/ImageProcessor.v ; ;
; Sdram_Control_4Port/Sdram_Params.h ; yes ; User Unspecified File ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_Params.h ; ;
; Sdram_Control_4Port/Sdram_Control_4Port.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_Control_4Port.v ; ;
; Sdram_Control_4Port/sdr_data_path.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/sdr_data_path.v ; ;
; Sdram_Control_4Port/control_interface.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/control_interface.v ; ;
; Sdram_Control_4Port/command.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/command.v ; ;
; Sdram_Control_4Port/Sdram_WR_FIFO.v ; yes ; User Wizard-Generated File ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_WR_FIFO.v ; ;
; Sdram_Control_4Port/Sdram_RD_FIFO.v ; yes ; User Wizard-Generated File ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_RD_FIFO.v ; ;
; Sdram_Control_4Port/Sdram_PLL.v ; yes ; User Wizard-Generated File ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_PLL.v ; Sdram_PLL ;
; Sdram_Control_4Port/Sdram_PLL/Sdram_PLL_0002.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_PLL/Sdram_PLL_0002.v ; Sdram_PLL ;
; v/YUV422_to_444.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/v/YUV422_to_444.v ; ;
; v/YCbCr2RGB.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/v/YCbCr2RGB.v ; ;
; v/VGA_Ctrl.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/v/VGA_Ctrl.v ; ;
; v/TD_Detect.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/v/TD_Detect.v ; ;
; v/Reset_Delay.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/v/Reset_Delay.v ; ;
; v/ITU_656_Decoder.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/v/ITU_656_Decoder.v ; ;
; v/I2C_Controller.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/v/I2C_Controller.v ; ;
; v/I2C_AV_Config.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/v/I2C_AV_Config.v ; ;
; v/Line_Buffer.v ; yes ; User Wizard-Generated File ; D:/School/ECE 241/Project0.85/v/Line_Buffer.v ; ;
; v/DIV.v ; yes ; User Wizard-Generated File ; D:/School/ECE 241/Project0.85/v/DIV.v ; ;
; v/AUDIO_DAC.v ; yes ; User Verilog HDL File ; D:/School/ECE 241/Project0.85/v/AUDIO_DAC.v ; ;
; lpm_divide.tdf ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/lpm_divide.tdf ; ;
; abs_divider.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/abs_divider.inc ; ;
; sign_div_unsign.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/sign_div_unsign.inc ; ;
; aglobal130.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/aglobal130.inc ; ;
; db/lpm_divide_h3t.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/lpm_divide_h3t.tdf ; ;
; db/sign_div_unsign_3li.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/sign_div_unsign_3li.tdf ; ;
; db/alt_u_div_tuf.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/alt_u_div_tuf.tdf ; ;
; altera_pll.v ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/altera_pll.v ; ;
; dcfifo.tdf ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/dcfifo.tdf ; ;
; lpm_counter.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/lpm_counter.inc ; ;
; lpm_add_sub.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
; altdpram.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/altdpram.inc ; ;
; a_graycounter.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/a_graycounter.inc ; ;
; a_fefifo.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/a_fefifo.inc ; ;
; a_gray2bin.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/a_gray2bin.inc ; ;
; dffpipe.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/dffpipe.inc ; ;
; alt_sync_fifo.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/alt_sync_fifo.inc ; ;
; lpm_compare.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/lpm_compare.inc ; ;
; altsyncram_fifo.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/altsyncram_fifo.inc ; ;
; db/dcfifo_bg02.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/dcfifo_bg02.tdf ; ;
; db/a_gray2bin_oab.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/a_gray2bin_oab.tdf ; ;
; db/a_graycounter_nv6.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/a_graycounter_nv6.tdf ; ;
; db/a_graycounter_jdc.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/a_graycounter_jdc.tdf ; ;
; db/altsyncram_jnb1.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/altsyncram_jnb1.tdf ; ;
; db/dffpipe_oe9.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/dffpipe_oe9.tdf ; ;
; db/alt_synch_pipe_vd8.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/alt_synch_pipe_vd8.tdf ; ;
; db/dffpipe_pe9.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/dffpipe_pe9.tdf ; ;
; db/alt_synch_pipe_0e8.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/alt_synch_pipe_0e8.tdf ; ;
; db/dffpipe_qe9.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/dffpipe_qe9.tdf ; ;
; db/cmpr_906.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/cmpr_906.tdf ; ;
; altsyncram.tdf ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/altsyncram.tdf ; ;
; stratix_ram_block.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
; lpm_mux.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/lpm_mux.inc ; ;
; lpm_decode.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/lpm_decode.inc ; ;
; a_rdenreg.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
; altrom.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/altrom.inc ; ;
; altram.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/altram.inc ; ;
; db/altsyncram_qnp2.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/altsyncram_qnp2.tdf ; ;
; batF1.mif ; yes ; Auto-Found Memory Initialization File ; D:/School/ECE 241/Project0.85/batF1.mif ; ;
; db/altsyncram_rnp2.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/altsyncram_rnp2.tdf ; ;
; batF2.mif ; yes ; Auto-Found Memory Initialization File ; D:/School/ECE 241/Project0.85/batF2.mif ; ;
; db/altsyncram_b6g1.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/altsyncram_b6g1.tdf ; ;
; smallerCave.mif ; yes ; Auto-Found Memory Initialization File ; D:/School/ECE 241/Project0.85/smallerCave.mif ; ;
; db/decode_m2a.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/decode_m2a.tdf ; ;
; db/mux_oib.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/mux_oib.tdf ; ;
; db/altsyncram_akg1.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/altsyncram_akg1.tdf ; ;
; FinalTitleScreen.mif ; yes ; Auto-Found Memory Initialization File ; D:/School/ECE 241/Project0.85/FinalTitleScreen.mif ; ;
; db/altsyncram_4bg1.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/altsyncram_4bg1.tdf ; ;
; Reticle.mif ; yes ; Auto-Found Memory Initialization File ; D:/School/ECE 241/Project0.85/Reticle.mif ; ;
; altshift_taps.tdf ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/altshift_taps.tdf ; ;
; lpm_constant.inc ; yes ; Megafunction ; d:/programs/altera/13.0/quartus/libraries/megafunctions/lpm_constant.inc ; ;
; db/shift_taps_9c61.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/shift_taps_9c61.tdf ; ;
; db/altsyncram_ffj1.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/altsyncram_ffj1.tdf ; ;
; db/cntr_lmf.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/cntr_lmf.tdf ; ;
; db/cmpr_pac.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/cmpr_pac.tdf ; ;
; db/cntr_b6h.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/cntr_b6h.tdf ; ;
; db/lpm_divide_p3m.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/lpm_divide_p3m.tdf ; ;
; db/sign_div_unsign_tlh.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/sign_div_unsign_tlh.tdf ; ;
; db/alt_u_div_pve.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/alt_u_div_pve.tdf ; ;
; db/lpm_divide_62m.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/lpm_divide_62m.tdf ; ;
; db/sign_div_unsign_9kh.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/sign_div_unsign_9kh.tdf ; ;
; db/alt_u_div_ose.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/alt_u_div_ose.tdf ; ;
; db/lpm_divide_jbm.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/lpm_divide_jbm.tdf ; ;
; db/lpm_divide_3am.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/lpm_divide_3am.tdf ; ;
; db/lpm_divide_gbm.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/lpm_divide_gbm.tdf ; ;
; db/sign_div_unsign_mlh.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/sign_div_unsign_mlh.tdf ; ;
; db/alt_u_div_ive.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/alt_u_div_ive.tdf ; ;
; db/lpm_divide_ibm.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/lpm_divide_ibm.tdf ; ;
; db/sign_div_unsign_olh.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/sign_div_unsign_olh.tdf ; ;
; db/alt_u_div_mve.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/alt_u_div_mve.tdf ; ;
; db/lpm_divide_m3m.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/lpm_divide_m3m.tdf ; ;
; db/sign_div_unsign_qlh.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/sign_div_unsign_qlh.tdf ; ;
; db/alt_u_div_ove.tdf ; yes ; Auto-Generated Megafunction ; D:/School/ECE 241/Project0.85/db/alt_u_div_ove.tdf ; ;
+------------------------------------------------+-----------------+----------------------------------------+-------------------------------------------------------------------------------+-----------+
+--------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+----------------+
; Resource ; Usage ;
+---------------------------------------------+----------------+
; Estimate of Logic utilization (ALMs needed) ; 4335 ;
; ; ;
; Combinational ALUT usage for logic ; 7673 ;
; -- 7 input functions ; 59 ;
; -- 6 input functions ; 822 ;
; -- 5 input functions ; 1187 ;
; -- 4 input functions ; 1107 ;
; -- <=3 input functions ; 4498 ;
; ; ;
; Dedicated logic registers ; 2707 ;
; ; ;
; I/O pins ; 168 ;
; Total MLAB memory bits ; 0 ;
; Total block memory bits ; 2428280 ;
; Total DSP Blocks ; 19 ;
; Total PLLs ; 3 ;
; -- PLLs ; 3 ;
; ; ;
; Maximum fan-out node ; TD_CLK27~input ;
; Maximum fan-out ; 2676 ;
; Total fan-out ; 46841 ;
; Average fan-out ; 4.14 ;
+---------------------------------------------+----------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+--------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |DE1_SoC_TV ; 7673 (1688) ; 2707 (24) ; 2428280 ; 19 ; 168 ; 0 ; |DE1_SoC_TV ; work ;
; |AUDIO_DAC:u12| ; 15 (15) ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|AUDIO_DAC:u12 ; work ;
; |Background2:background| ; 16 (0) ; 8 (0) ; 1572864 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Background2:background ; work ;
; |altsyncram:altsyncram_component| ; 16 (0) ; 8 (0) ; 1572864 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Background2:background|altsyncram:altsyncram_component ; work ;
; |altsyncram_b6g1:auto_generated| ; 16 (0) ; 8 (8) ; 1572864 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Background2:background|altsyncram:altsyncram_component|altsyncram_b6g1:auto_generated ; work ;
; |decode_m2a:rden_decode| ; 16 (16) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Background2:background|altsyncram:altsyncram_component|altsyncram_b6g1:auto_generated|decode_m2a:rden_decode ; work ;
; |Cursor:Cursor1| ; 739 (84) ; 399 (23) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1 ; work ;
; |ImageProcessor:imProcG| ; 332 (138) ; 188 (188) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcG ; work ;
; |lpm_divide:Div0| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcG|lpm_divide:Div0 ; work ;
; |lpm_divide_ibm:auto_generated| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcG|lpm_divide:Div0|lpm_divide_ibm:auto_generated ; work ;
; |sign_div_unsign_olh:divider| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcG|lpm_divide:Div0|lpm_divide_ibm:auto_generated|sign_div_unsign_olh:divider ; work ;
; |alt_u_div_mve:divider| ; 97 (97) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcG|lpm_divide:Div0|lpm_divide_ibm:auto_generated|sign_div_unsign_olh:divider|alt_u_div_mve:divider ; work ;
; |lpm_divide:Div1| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcG|lpm_divide:Div1 ; work ;
; |lpm_divide_ibm:auto_generated| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcG|lpm_divide:Div1|lpm_divide_ibm:auto_generated ; work ;
; |sign_div_unsign_olh:divider| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcG|lpm_divide:Div1|lpm_divide_ibm:auto_generated|sign_div_unsign_olh:divider ; work ;
; |alt_u_div_mve:divider| ; 97 (97) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcG|lpm_divide:Div1|lpm_divide_ibm:auto_generated|sign_div_unsign_olh:divider|alt_u_div_mve:divider ; work ;
; |ImageProcessor:imProcR| ; 323 (129) ; 188 (188) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcR ; work ;
; |lpm_divide:Div0| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcR|lpm_divide:Div0 ; work ;
; |lpm_divide_ibm:auto_generated| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcR|lpm_divide:Div0|lpm_divide_ibm:auto_generated ; work ;
; |sign_div_unsign_olh:divider| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcR|lpm_divide:Div0|lpm_divide_ibm:auto_generated|sign_div_unsign_olh:divider ; work ;
; |alt_u_div_mve:divider| ; 97 (97) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcR|lpm_divide:Div0|lpm_divide_ibm:auto_generated|sign_div_unsign_olh:divider|alt_u_div_mve:divider ; work ;
; |lpm_divide:Div1| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcR|lpm_divide:Div1 ; work ;
; |lpm_divide_ibm:auto_generated| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcR|lpm_divide:Div1|lpm_divide_ibm:auto_generated ; work ;
; |sign_div_unsign_olh:divider| ; 97 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcR|lpm_divide:Div1|lpm_divide_ibm:auto_generated|sign_div_unsign_olh:divider ; work ;
; |alt_u_div_mve:divider| ; 97 (97) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Cursor:Cursor1|ImageProcessor:imProcR|lpm_divide:Div1|lpm_divide_ibm:auto_generated|sign_div_unsign_olh:divider|alt_u_div_mve:divider ; work ;
; |DIV:u5| ; 48 (0) ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|DIV:u5 ; work ;
; |lpm_divide:LPM_DIVIDE_component| ; 48 (0) ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|DIV:u5|lpm_divide:LPM_DIVIDE_component ; work ;
; |lpm_divide_h3t:auto_generated| ; 48 (0) ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|DIV:u5|lpm_divide:LPM_DIVIDE_component|lpm_divide_h3t:auto_generated ; work ;
; |sign_div_unsign_3li:divider| ; 48 (0) ; 10 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|DIV:u5|lpm_divide:LPM_DIVIDE_component|lpm_divide_h3t:auto_generated|sign_div_unsign_3li:divider ; work ;
; |alt_u_div_tuf:divider| ; 48 (48) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|DIV:u5|lpm_divide:LPM_DIVIDE_component|lpm_divide_h3t:auto_generated|sign_div_unsign_3li:divider|alt_u_div_tuf:divider ; work ;
; |I2C_AV_Config:u1| ; 104 (58) ; 75 (45) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|I2C_AV_Config:u1 ; work ;
; |I2C_Controller:u0| ; 46 (46) ; 30 (30) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|I2C_AV_Config:u1|I2C_Controller:u0 ; work ;
; |ITU_656_Decoder:u4| ; 38 (38) ; 80 (80) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|ITU_656_Decoder:u4 ; work ;
; |Line_Buffer:u10| ; 34 (0) ; 21 (0) ; 10208 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u10 ; work ;
; |altshift_taps:ALTSHIFT_TAPS_component| ; 34 (0) ; 21 (0) ; 10208 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u10|altshift_taps:ALTSHIFT_TAPS_component ; work ;
; |shift_taps_9c61:auto_generated| ; 34 (1) ; 21 (1) ; 10208 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u10|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated ; work ;
; |altsyncram_ffj1:altsyncram2| ; 0 (0) ; 0 (0) ; 10208 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u10|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|altsyncram_ffj1:altsyncram2 ; work ;
; |cntr_b6h:cntr3| ; 19 (19) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u10|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|cntr_b6h:cntr3 ; work ;
; |cntr_lmf:cntr1| ; 14 (12) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u10|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|cntr_lmf:cntr1 ; work ;
; |cmpr_pac:cmpr6| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u10|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|cntr_lmf:cntr1|cmpr_pac:cmpr6 ; work ;
; |Line_Buffer:u11| ; 34 (0) ; 21 (0) ; 10208 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u11 ; work ;
; |altshift_taps:ALTSHIFT_TAPS_component| ; 34 (0) ; 21 (0) ; 10208 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u11|altshift_taps:ALTSHIFT_TAPS_component ; work ;
; |shift_taps_9c61:auto_generated| ; 34 (1) ; 21 (1) ; 10208 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u11|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated ; work ;
; |altsyncram_ffj1:altsyncram2| ; 0 (0) ; 0 (0) ; 10208 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u11|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|altsyncram_ffj1:altsyncram2 ; work ;
; |cntr_b6h:cntr3| ; 19 (19) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u11|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|cntr_b6h:cntr3 ; work ;
; |cntr_lmf:cntr1| ; 14 (12) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u11|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|cntr_lmf:cntr1 ; work ;
; |cmpr_pac:cmpr6| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Line_Buffer:u11|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|cntr_lmf:cntr1|cmpr_pac:cmpr6 ; work ;
; |Reset_Delay:u3| ; 32 (32) ; 25 (25) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Reset_Delay:u3 ; work ;
; |Reticle:reticle| ; 0 (0) ; 0 (0) ; 15000 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Reticle:reticle ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 15000 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Reticle:reticle|altsyncram:altsyncram_component ; work ;
; |altsyncram_4bg1:auto_generated| ; 0 (0) ; 0 (0) ; 15000 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Reticle:reticle|altsyncram:altsyncram_component|altsyncram_4bg1:auto_generated ; work ;
; |Sdram_Control_4Port:u6| ; 547 (198) ; 574 (127) ; 24608 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6 ; work ;
; |Sdram_PLL:sdram_pll1| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1 ; Sdram_PLL ;
; |Sdram_PLL_0002:sdram_pll_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|Sdram_PLL_0002:sdram_pll_inst ; Sdram_PLL ;
; |altera_pll:altera_pll_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|Sdram_PLL_0002:sdram_pll_inst|altera_pll:altera_pll_i ; work ;
; |Sdram_RD_FIFO:read_fifo1| ; 73 (0) ; 114 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1 ; work ;
; |dcfifo:dcfifo_component| ; 73 (0) ; 114 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component ; work ;
; |dcfifo_bg02:auto_generated| ; 73 (15) ; 114 (30) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated ; work ;
; |a_gray2bin_oab:wrptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_gray2bin_oab:wrptr_g_gray2bin ; work ;
; |a_gray2bin_oab:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_gray2bin_oab:ws_dgrp_gray2bin ; work ;
; |a_graycounter_jdc:wrptr_g1p| ; 15 (15) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p ; work ;
; |a_graycounter_nv6:rdptr_g1p| ; 17 (17) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_nv6:rdptr_g1p ; work ;
; |alt_synch_pipe_0e8:ws_dgrp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp ; work ;
; |dffpipe_qe9:dffpipe16| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ;
; |alt_synch_pipe_vd8:rs_dgwp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp ; work ;
; |dffpipe_pe9:dffpipe13| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ;
; |altsyncram_jnb1:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram ; work ;
; |cmpr_906:rdempty_eq_comp| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|cmpr_906:rdempty_eq_comp ; work ;
; |cmpr_906:wrfull_eq_comp| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|cmpr_906:wrfull_eq_comp ; work ;
; |dffpipe_oe9:ws_brp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_brp ; work ;
; |dffpipe_oe9:ws_bwp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_bwp ; work ;
; |Sdram_RD_FIFO:read_fifo2| ; 73 (0) ; 114 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2 ; work ;
; |dcfifo:dcfifo_component| ; 73 (0) ; 114 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component ; work ;
; |dcfifo_bg02:auto_generated| ; 73 (15) ; 114 (30) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated ; work ;
; |a_gray2bin_oab:wrptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_gray2bin_oab:wrptr_g_gray2bin ; work ;
; |a_gray2bin_oab:ws_dgrp_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_gray2bin_oab:ws_dgrp_gray2bin ; work ;
; |a_graycounter_jdc:wrptr_g1p| ; 15 (15) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p ; work ;
; |a_graycounter_nv6:rdptr_g1p| ; 17 (17) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_nv6:rdptr_g1p ; work ;
; |alt_synch_pipe_0e8:ws_dgrp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp ; work ;
; |dffpipe_qe9:dffpipe16| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ;
; |alt_synch_pipe_vd8:rs_dgwp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp ; work ;
; |dffpipe_pe9:dffpipe13| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ;
; |altsyncram_jnb1:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram ; work ;
; |cmpr_906:rdempty_eq_comp| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|cmpr_906:rdempty_eq_comp ; work ;
; |cmpr_906:wrfull_eq_comp| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|cmpr_906:wrfull_eq_comp ; work ;
; |dffpipe_oe9:ws_brp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_brp ; work ;
; |dffpipe_oe9:ws_bwp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_bwp ; work ;
; |Sdram_WR_FIFO:write_fifo1| ; 73 (0) ; 114 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1 ; work ;
; |dcfifo:dcfifo_component| ; 73 (0) ; 114 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component ; work ;
; |dcfifo_bg02:auto_generated| ; 73 (15) ; 114 (30) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated ; work ;
; |a_gray2bin_oab:rdptr_g_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_gray2bin_oab:rdptr_g_gray2bin ; work ;
; |a_gray2bin_oab:rs_dgwp_gray2bin| ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_gray2bin_oab:rs_dgwp_gray2bin ; work ;
; |a_graycounter_jdc:wrptr_g1p| ; 15 (15) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p ; work ;
; |a_graycounter_nv6:rdptr_g1p| ; 17 (17) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_nv6:rdptr_g1p ; work ;
; |alt_synch_pipe_0e8:ws_dgrp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp ; work ;
; |dffpipe_qe9:dffpipe16| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16 ; work ;
; |alt_synch_pipe_vd8:rs_dgwp| ; 0 (0) ; 20 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp ; work ;
; |dffpipe_pe9:dffpipe13| ; 0 (0) ; 20 (20) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe13 ; work ;
; |altsyncram_jnb1:fifo_ram| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram ; work ;
; |cmpr_906:rdempty_eq_comp| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|cmpr_906:rdempty_eq_comp ; work ;
; |cmpr_906:wrfull_eq_comp| ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|cmpr_906:wrfull_eq_comp ; work ;
; |dffpipe_oe9:rs_brp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_brp ; work ;
; |dffpipe_oe9:rs_bwp| ; 0 (0) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_bwp ; work ;
; |Sdram_WR_FIFO:write_fifo2| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2 ; work ;
; |dcfifo:dcfifo_component| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component ; work ;
; |dcfifo_bg02:auto_generated| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated ; work ;
; |altsyncram_jnb1:fifo_ram| ; 0 (0) ; 0 (0) ; 32 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram ; work ;
; |command:command1| ; 55 (55) ; 49 (49) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|command:command1 ; work ;
; |control_interface:control1| ; 75 (75) ; 56 (56) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Sdram_Control_4Port:u6|control_interface:control1 ; work ;
; |Shooter:gameLogic| ; 3261 (351) ; 1373 (103) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic ; work ;
; |Target:T10| ; 291 (137) ; 127 (72) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T10 ; work ;
; |LFSR:randomGenerator1| ; 22 (22) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T10|LFSR:randomGenerator1 ; work ;
; |LFSR:randomGenerator2| ; 19 (19) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T10|LFSR:randomGenerator2 ; work ;
; |lpm_divide:Mod0| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T10|lpm_divide:Mod0 ; work ;
; |lpm_divide_m3m:auto_generated| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T10|lpm_divide:Mod0|lpm_divide_m3m:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T10|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_ove:divider| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T10|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_ove:divider ; work ;
; |Target:T1| ; 287 (136) ; 127 (72) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T1 ; work ;
; |LFSR:randomGenerator1| ; 19 (19) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T1|LFSR:randomGenerator1 ; work ;
; |LFSR:randomGenerator2| ; 19 (19) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T1|LFSR:randomGenerator2 ; work ;
; |lpm_divide:Mod0| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T1|lpm_divide:Mod0 ; work ;
; |lpm_divide_m3m:auto_generated| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T1|lpm_divide:Mod0|lpm_divide_m3m:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T1|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_ove:divider| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T1|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_ove:divider ; work ;
; |Target:T2| ; 289 (137) ; 127 (72) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T2 ; work ;
; |LFSR:randomGenerator1| ; 20 (20) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T2|LFSR:randomGenerator1 ; work ;
; |LFSR:randomGenerator2| ; 19 (19) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T2|LFSR:randomGenerator2 ; work ;
; |lpm_divide:Mod0| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T2|lpm_divide:Mod0 ; work ;
; |lpm_divide_m3m:auto_generated| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T2|lpm_divide:Mod0|lpm_divide_m3m:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T2|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_ove:divider| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T2|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_ove:divider ; work ;
; |Target:T3| ; 290 (137) ; 127 (72) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T3 ; work ;
; |LFSR:randomGenerator1| ; 21 (21) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T3|LFSR:randomGenerator1 ; work ;
; |LFSR:randomGenerator2| ; 19 (19) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T3|LFSR:randomGenerator2 ; work ;
; |lpm_divide:Mod0| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T3|lpm_divide:Mod0 ; work ;
; |lpm_divide_m3m:auto_generated| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T3|lpm_divide:Mod0|lpm_divide_m3m:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T3|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_ove:divider| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T3|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_ove:divider ; work ;
; |Target:T4| ; 288 (137) ; 127 (72) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T4 ; work ;
; |LFSR:randomGenerator1| ; 20 (20) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T4|LFSR:randomGenerator1 ; work ;
; |LFSR:randomGenerator2| ; 18 (18) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T4|LFSR:randomGenerator2 ; work ;
; |lpm_divide:Mod0| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T4|lpm_divide:Mod0 ; work ;
; |lpm_divide_m3m:auto_generated| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T4|lpm_divide:Mod0|lpm_divide_m3m:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T4|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_ove:divider| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T4|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_ove:divider ; work ;
; |Target:T5| ; 288 (137) ; 127 (72) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T5 ; work ;
; |LFSR:randomGenerator1| ; 20 (20) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T5|LFSR:randomGenerator1 ; work ;
; |LFSR:randomGenerator2| ; 18 (18) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T5|LFSR:randomGenerator2 ; work ;
; |lpm_divide:Mod0| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T5|lpm_divide:Mod0 ; work ;
; |lpm_divide_m3m:auto_generated| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T5|lpm_divide:Mod0|lpm_divide_m3m:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T5|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_ove:divider| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T5|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_ove:divider ; work ;
; |Target:T6| ; 297 (137) ; 127 (72) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T6 ; work ;
; |LFSR:randomGenerator1| ; 24 (24) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T6|LFSR:randomGenerator1 ; work ;
; |LFSR:randomGenerator2| ; 23 (23) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T6|LFSR:randomGenerator2 ; work ;
; |lpm_divide:Mod0| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T6|lpm_divide:Mod0 ; work ;
; |lpm_divide_m3m:auto_generated| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T6|lpm_divide:Mod0|lpm_divide_m3m:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T6|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_ove:divider| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T6|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_ove:divider ; work ;
; |Target:T7| ; 291 (137) ; 127 (72) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T7 ; work ;
; |LFSR:randomGenerator1| ; 20 (20) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T7|LFSR:randomGenerator1 ; work ;
; |LFSR:randomGenerator2| ; 21 (21) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T7|LFSR:randomGenerator2 ; work ;
; |lpm_divide:Mod0| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T7|lpm_divide:Mod0 ; work ;
; |lpm_divide_m3m:auto_generated| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T7|lpm_divide:Mod0|lpm_divide_m3m:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T7|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_ove:divider| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T7|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_ove:divider ; work ;
; |Target:T8| ; 291 (137) ; 127 (72) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T8 ; work ;
; |LFSR:randomGenerator1| ; 20 (20) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T8|LFSR:randomGenerator1 ; work ;
; |LFSR:randomGenerator2| ; 21 (21) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T8|LFSR:randomGenerator2 ; work ;
; |lpm_divide:Mod0| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T8|lpm_divide:Mod0 ; work ;
; |lpm_divide_m3m:auto_generated| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T8|lpm_divide:Mod0|lpm_divide_m3m:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T8|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_ove:divider| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T8|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_ove:divider ; work ;
; |Target:T9| ; 298 (137) ; 127 (72) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T9 ; work ;
; |LFSR:randomGenerator1| ; 27 (27) ; 22 (22) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T9|LFSR:randomGenerator1 ; work ;
; |LFSR:randomGenerator2| ; 21 (21) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T9|LFSR:randomGenerator2 ; work ;
; |lpm_divide:Mod0| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T9|lpm_divide:Mod0 ; work ;
; |lpm_divide_m3m:auto_generated| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T9|lpm_divide:Mod0|lpm_divide_m3m:auto_generated ; work ;
; |sign_div_unsign_qlh:divider| ; 113 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T9|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider ; work ;
; |alt_u_div_ove:divider| ; 113 (113) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|Shooter:gameLogic|Target:T9|lpm_divide:Mod0|lpm_divide_m3m:auto_generated|sign_div_unsign_qlh:divider|alt_u_div_ove:divider ; work ;
; |TD_Detect:u2| ; 13 (13) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TD_Detect:u2 ; work ;
; |TScreen:title| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TScreen:title ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TScreen:title|altsyncram:altsyncram_component ; work ;
; |altsyncram_akg1:auto_generated| ; 0 (0) ; 0 (0) ; 8192 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TScreen:title|altsyncram:altsyncram_component|altsyncram_akg1:auto_generated ; work ;
; |TimeDisplayController:timeController| ; 396 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController ; work ;
; |lpm_divide:Div0| ; 102 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div0 ; work ;
; |lpm_divide_jbm:auto_generated| ; 102 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div0|lpm_divide_jbm:auto_generated ; work ;
; |sign_div_unsign_tlh:divider| ; 102 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div0|lpm_divide_jbm:auto_generated|sign_div_unsign_tlh:divider ; work ;
; |alt_u_div_pve:divider| ; 102 (102) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div0|lpm_divide_jbm:auto_generated|sign_div_unsign_tlh:divider|alt_u_div_pve:divider ; work ;
; |lpm_divide:Div1| ; 27 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div1 ; work ;
; |lpm_divide_3am:auto_generated| ; 27 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div1|lpm_divide_3am:auto_generated ; work ;
; |sign_div_unsign_9kh:divider| ; 27 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div1|lpm_divide_3am:auto_generated|sign_div_unsign_9kh:divider ; work ;
; |alt_u_div_ose:divider| ; 27 (27) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div1|lpm_divide_3am:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_ose:divider ; work ;
; |lpm_divide:Div2| ; 25 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div2 ; work ;
; |lpm_divide_3am:auto_generated| ; 25 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div2|lpm_divide_3am:auto_generated ; work ;
; |sign_div_unsign_9kh:divider| ; 25 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div2|lpm_divide_3am:auto_generated|sign_div_unsign_9kh:divider ; work ;
; |alt_u_div_ose:divider| ; 25 (25) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Div2|lpm_divide_3am:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_ose:divider ; work ;
; |lpm_divide:Mod0| ; 31 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod0 ; work ;
; |lpm_divide_62m:auto_generated| ; 31 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod0|lpm_divide_62m:auto_generated ; work ;
; |sign_div_unsign_9kh:divider| ; 31 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod0|lpm_divide_62m:auto_generated|sign_div_unsign_9kh:divider ; work ;
; |alt_u_div_ose:divider| ; 31 (31) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod0|lpm_divide_62m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_ose:divider ; work ;
; |lpm_divide:Mod1| ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod1 ; work ;
; |lpm_divide_62m:auto_generated| ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod1|lpm_divide_62m:auto_generated ; work ;
; |sign_div_unsign_9kh:divider| ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod1|lpm_divide_62m:auto_generated|sign_div_unsign_9kh:divider ; work ;
; |alt_u_div_ose:divider| ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod1|lpm_divide_62m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_ose:divider ; work ;
; |lpm_divide:Mod2| ; 118 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod2 ; work ;
; |lpm_divide_p3m:auto_generated| ; 118 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod2|lpm_divide_p3m:auto_generated ; work ;
; |sign_div_unsign_tlh:divider| ; 118 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod2|lpm_divide_p3m:auto_generated|sign_div_unsign_tlh:divider ; work ;
; |alt_u_div_pve:divider| ; 118 (118) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod2|lpm_divide_p3m:auto_generated|sign_div_unsign_tlh:divider|alt_u_div_pve:divider ; work ;
; |lpm_divide:Mod3| ; 29 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod3 ; work ;
; |lpm_divide_62m:auto_generated| ; 29 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod3|lpm_divide_62m:auto_generated ; work ;
; |sign_div_unsign_9kh:divider| ; 29 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod3|lpm_divide_62m:auto_generated|sign_div_unsign_9kh:divider ; work ;
; |alt_u_div_ose:divider| ; 29 (29) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod3|lpm_divide_62m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_ose:divider ; work ;
; |lpm_divide:Mod4| ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod4 ; work ;
; |lpm_divide_62m:auto_generated| ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod4|lpm_divide_62m:auto_generated ; work ;
; |sign_div_unsign_9kh:divider| ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod4|lpm_divide_62m:auto_generated|sign_div_unsign_9kh:divider ; work ;
; |alt_u_div_ose:divider| ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|TimeDisplayController:timeController|lpm_divide:Mod4|lpm_divide_62m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_ose:divider ; work ;
; |VGA_Ctrl:u9| ; 75 (75) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|VGA_Ctrl:u9 ; work ;
; |YCbCr2RGB:u8| ; 105 (105) ; 24 (24) ; 0 ; 8 ; 0 ; 0 ; |DE1_SoC_TV|YCbCr2RGB:u8 ; work ;
; |YUV422_to_444:u7| ; 0 (0) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|YUV422_to_444:u7 ; work ;
; |lpm_divide:Div15| ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div15 ; work ;
; |lpm_divide_gbm:auto_generated| ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div15|lpm_divide_gbm:auto_generated ; work ;
; |sign_div_unsign_mlh:divider| ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div15|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider ; work ;
; |alt_u_div_ive:divider| ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div15|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider|alt_u_div_ive:divider ; work ;
; |lpm_divide:Div23| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div23 ; work ;
; |lpm_divide_gbm:auto_generated| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div23|lpm_divide_gbm:auto_generated ; work ;
; |sign_div_unsign_mlh:divider| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div23|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider ; work ;
; |alt_u_div_ive:divider| ; 61 (61) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div23|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider|alt_u_div_ive:divider ; work ;
; |lpm_divide:Div31| ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div31 ; work ;
; |lpm_divide_gbm:auto_generated| ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div31|lpm_divide_gbm:auto_generated ; work ;
; |sign_div_unsign_mlh:divider| ; 60 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div31|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider ; work ;
; |alt_u_div_ive:divider| ; 60 (60) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div31|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider|alt_u_div_ive:divider ; work ;
; |lpm_divide:Div38| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div38 ; work ;
; |lpm_divide_gbm:auto_generated| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div38|lpm_divide_gbm:auto_generated ; work ;
; |sign_div_unsign_mlh:divider| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div38|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider ; work ;
; |alt_u_div_ive:divider| ; 61 (61) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div38|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider|alt_u_div_ive:divider ; work ;
; |lpm_divide:Div39| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div39 ; work ;
; |lpm_divide_gbm:auto_generated| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div39|lpm_divide_gbm:auto_generated ; work ;
; |sign_div_unsign_mlh:divider| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div39|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider ; work ;
; |alt_u_div_ive:divider| ; 61 (61) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div39|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider|alt_u_div_ive:divider ; work ;
; |lpm_divide:Div7| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div7 ; work ;
; |lpm_divide_gbm:auto_generated| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div7|lpm_divide_gbm:auto_generated ; work ;
; |sign_div_unsign_mlh:divider| ; 61 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div7|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider ; work ;
; |alt_u_div_ive:divider| ; 61 (61) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|lpm_divide:Div7|lpm_divide_gbm:auto_generated|sign_div_unsign_mlh:divider|alt_u_div_ive:divider ; work ;
; |multiFrameStorage:frame1| ; 164 (164) ; 0 (0) ; 787200 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1 ; work ;
; |frameStorage:FS10| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS10 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS10|altsyncram:altsyncram_component ; work ;
; |altsyncram_rnp2:auto_generated| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS10|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated ; work ;
; |frameStorage:FS1| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS1 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS1|altsyncram:altsyncram_component ; work ;
; |altsyncram_qnp2:auto_generated| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS1|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated ; work ;
; |frameStorage:FS2| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS2 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS2|altsyncram:altsyncram_component ; work ;
; |altsyncram_qnp2:auto_generated| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS2|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated ; work ;
; |frameStorage:FS3| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS3 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS3|altsyncram:altsyncram_component ; work ;
; |altsyncram_qnp2:auto_generated| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS3|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated ; work ;
; |frameStorage:FS4| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS4 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS4|altsyncram:altsyncram_component ; work ;
; |altsyncram_qnp2:auto_generated| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS4|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated ; work ;
; |frameStorage:FS5| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS5 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS5|altsyncram:altsyncram_component ; work ;
; |altsyncram_qnp2:auto_generated| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS5|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated ; work ;
; |frameStorage:FS6| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS6 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS6|altsyncram:altsyncram_component ; work ;
; |altsyncram_rnp2:auto_generated| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS6|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated ; work ;
; |frameStorage:FS7| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS7 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS7|altsyncram:altsyncram_component ; work ;
; |altsyncram_rnp2:auto_generated| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS7|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated ; work ;
; |frameStorage:FS8| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS8 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS8|altsyncram:altsyncram_component ; work ;
; |altsyncram_rnp2:auto_generated| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS8|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated ; work ;
; |frameStorage:FS9| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS9 ; work ;
; |altsyncram:altsyncram_component| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS9|altsyncram:altsyncram_component ; work ;
; |altsyncram_rnp2:auto_generated| ; 0 (0) ; 0 (0) ; 78720 ; 0 ; 0 ; 0 ; |DE1_SoC_TV|multiFrameStorage:frame1|frameStorage:FS9|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated ; work ;
+--------------------------------------------------+-------------------+--------------+-------------------+------------+------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary ;
+-----------------------------------------------------------------------------------------------------------------------------------------+------------+------------------+--------------+--------------+--------------+--------------+---------+----------------------+
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
+-----------------------------------------------------------------------------------------------------------------------------------------+------------+------------------+--------------+--------------+--------------+--------------+---------+----------------------+
; Background2:background|altsyncram:altsyncram_component|altsyncram_b6g1:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 131072 ; 12 ; -- ; -- ; 1572864 ; smallerCave.mif ;
; Line_Buffer:u10|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|altsyncram_ffj1:altsyncram2|ALTSYNCRAM ; M10K block ; Simple Dual Port ; 638 ; 16 ; 638 ; 16 ; 10208 ; None ;
; Line_Buffer:u11|altshift_taps:ALTSHIFT_TAPS_component|shift_taps_9c61:auto_generated|altsyncram_ffj1:altsyncram2|ALTSYNCRAM ; M10K block ; Simple Dual Port ; 638 ; 16 ; 638 ; 16 ; 10208 ; None ;
; Reticle:reticle|altsyncram:altsyncram_component|altsyncram_4bg1:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 625 ; 24 ; -- ; -- ; 15000 ; Reticle.mif ;
; Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram|ALTSYNCRAM ; M10K block ; Simple Dual Port ; 512 ; 16 ; 512 ; 16 ; 8192 ; None ;
; Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram|ALTSYNCRAM ; M10K block ; Simple Dual Port ; 512 ; 16 ; 512 ; 16 ; 8192 ; None ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram|ALTSYNCRAM ; M10K block ; Simple Dual Port ; 512 ; 16 ; 512 ; 16 ; 8192 ; None ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|altsyncram_jnb1:fifo_ram|ALTSYNCRAM ; M10K block ; Simple Dual Port ; 512 ; 16 ; 512 ; 16 ; 8192 ; None ;
; TScreen:title|altsyncram:altsyncram_component|altsyncram_akg1:auto_generated|ALTSYNCRAM ; AUTO ; ROM ; 8192 ; 12 ; -- ; -- ; 98304 ; FinalTitleScreen.mif ;
; multiFrameStorage:frame1|frameStorage:FS10|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 3280 ; 24 ; 3280 ; 24 ; 78720 ; batF2.mif ;
; multiFrameStorage:frame1|frameStorage:FS1|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 3280 ; 24 ; 3280 ; 24 ; 78720 ; batF1.mif ;
; multiFrameStorage:frame1|frameStorage:FS2|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 3280 ; 24 ; 3280 ; 24 ; 78720 ; batF1.mif ;
; multiFrameStorage:frame1|frameStorage:FS3|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 3280 ; 24 ; 3280 ; 24 ; 78720 ; batF1.mif ;
; multiFrameStorage:frame1|frameStorage:FS4|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 3280 ; 24 ; 3280 ; 24 ; 78720 ; batF1.mif ;
; multiFrameStorage:frame1|frameStorage:FS5|altsyncram:altsyncram_component|altsyncram_qnp2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 3280 ; 24 ; 3280 ; 24 ; 78720 ; batF1.mif ;
; multiFrameStorage:frame1|frameStorage:FS6|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 3280 ; 24 ; 3280 ; 24 ; 78720 ; batF2.mif ;
; multiFrameStorage:frame1|frameStorage:FS7|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 3280 ; 24 ; 3280 ; 24 ; 78720 ; batF2.mif ;
; multiFrameStorage:frame1|frameStorage:FS8|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 3280 ; 24 ; 3280 ; 24 ; 78720 ; batF2.mif ;
; multiFrameStorage:frame1|frameStorage:FS9|altsyncram:altsyncram_component|altsyncram_rnp2:auto_generated|ALTSYNCRAM ; AUTO ; True Dual Port ; 3280 ; 24 ; 3280 ; 24 ; 78720 ; batF2.mif ;
+-----------------------------------------------------------------------------------------------------------------------------------------+------------+------------------+--------------+--------------+--------------+--------------+---------+----------------------+
+-----------------------------------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary ;
+---------------------+-------------+---------------------+-------------------+
; Statistic ; Number Used ; Available per Block ; Maximum Available ;
+---------------------+-------------+---------------------+-------------------+
; Independent 18x18 ; 19 ; 2.00 ; -- ;
; DSP Block ; 19 ; -- ; -- ;
; DSP 18-bit Element ; 19 ; 2.00 ; -- ;
; Unsigned Multiplier ; 19 ; -- ; -- ;
+---------------------+-------------+---------------------+-------------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary ;
+--------+----------------------------+---------+--------------+--------------+--------------------------------------------------------------+-------------------------------------------------------------------+
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
+--------+----------------------------+---------+--------------+--------------+--------------------------------------------------------------+-------------------------------------------------------------------+
; Altera ; ROM: 1-PORT ; N/A ; N/A ; N/A ; |DE1_SoC_TV|Background2:background ; D:/School/ECE 241/Project0.85/Background2.v ;
; Altera ; ROM: 1-PORT ; N/A ; N/A ; N/A ; |DE1_SoC_TV|TScreen:title ; D:/School/ECE 241/Project0.85/TScreen.v ;
; Altera ; LPM_DIVIDE ; 13.1 ; N/A ; N/A ; |DE1_SoC_TV|DIV:u5 ; D:/School/ECE 241/Project0.85/v/DIV.v ;
; Altera ; FIFO ; 13.1 ; N/A ; N/A ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1 ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_RD_FIFO.v ;
; Altera ; FIFO ; 13.1 ; N/A ; N/A ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2 ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_RD_FIFO.v ;
; Altera ; altera_pll ; 13.1 ; N/A ; N/A ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1 ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_PLL.v ;
; Altera ; FIFO ; 13.1 ; N/A ; N/A ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1 ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_WR_FIFO.v ;
; Altera ; FIFO ; 13.1 ; N/A ; N/A ; |DE1_SoC_TV|Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2 ; D:/School/ECE 241/Project0.85/Sdram_Control_4Port/Sdram_WR_FIFO.v ;
; Altera ; Shift register (RAM-based) ; 13.1 ; N/A ; N/A ; |DE1_SoC_TV|Line_Buffer:u10 ; D:/School/ECE 241/Project0.85/v/Line_Buffer.v ;
; Altera ; Shift register (RAM-based) ; 13.1 ; N/A ; N/A ; |DE1_SoC_TV|Line_Buffer:u11 ; D:/School/ECE 241/Project0.85/v/Line_Buffer.v ;
+--------+----------------------------+---------+--------------+--------------+--------------------------------------------------------------+-------------------------------------------------------------------+
Encoding Type: One-Hot
+-------------------------------------------------------------------+
; State Machine - |DE1_SoC_TV|I2C_AV_Config:u1|mSetup_ST ;
+----------------+----------------+----------------+----------------+
; Name ; mSetup_ST.0000 ; mSetup_ST.0010 ; mSetup_ST.0001 ;
+----------------+----------------+----------------+----------------+
; mSetup_ST.0000 ; 0 ; 0 ; 0 ;
; mSetup_ST.0001 ; 1 ; 0 ; 1 ;
; mSetup_ST.0010 ; 1 ; 1 ; 0 ;
+----------------+----------------+----------------+----------------+
Encoding Type: One-Hot
+--------------------------------------------------------------------------------------------------------------+
; State Machine - |DE1_SoC_TV|Shooter:gameLogic|currentState ;
+----------------------+---------------------+--------------------+---------------------+----------------------+
; Name ; currentState.LOSE_S ; currentState.END_S ; currentState.PLAY_S ; currentState.START_S ;
+----------------------+---------------------+--------------------+---------------------+----------------------+
; currentState.START_S ; 0 ; 0 ; 0 ; 0 ;
; currentState.PLAY_S ; 0 ; 0 ; 1 ; 1 ;
; currentState.END_S ; 0 ; 1 ; 0 ; 1 ;
; currentState.LOSE_S ; 1 ; 0 ; 0 ; 1 ;
+----------------------+---------------------+--------------------+---------------------+----------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name ; Reason for Removal ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+
; AUDIO_DAC:u12|FLASH_Out_Tmp[0..15] ; Stuck at GND due to stuck port data_in ;
; AUDIO_DAC:u12|FLASH_Out[0..15] ; Stuck at GND due to stuck port data_in ;
; AUDIO_DAC:u12|SDRAM_Out_Tmp[0..15] ; Stuck at GND due to stuck port data_in ;
; AUDIO_DAC:u12|SDRAM_Out[0..15] ; Stuck at GND due to stuck port data_in ;
; AUDIO_DAC:u12|SRAM_Out_Tmp[0..15] ; Stuck at GND due to stuck port data_in ;
; AUDIO_DAC:u12|SRAM_Out[0..15] ; Stuck at GND due to stuck port data_in ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[0] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[0] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[1] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[1] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[2] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[2] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[3] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[3] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[4] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[4] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[5] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[5] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[6] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[6] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[7] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[7] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[8] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[8] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe18a[9] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_0e8:ws_dgrp|dffpipe_qe9:dffpipe16|dffe17a[9] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|delayed_wrptr_g[0..9] ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|wrptr_g[0..9] ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe13|dffe14a[0..9] ; Stuck at GND due to stuck port data_in ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|alt_synch_pipe_vd8:rs_dgwp|dffpipe_pe9:dffpipe13|dffe15a[0..9] ; Stuck at GND due to stuck port data_in ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Stuck at GND due to stuck port data_in ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|counter8a0 ; Stuck at VCC due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|counter8a1 ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|counter8a2 ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|counter8a3 ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|counter8a4 ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|counter8a5 ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|counter8a6 ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|counter8a7 ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|counter8a8 ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|counter8a9 ; Stuck at GND due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|parity9 ; Stuck at VCC due to stuck port clock ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|a_graycounter_jdc:wrptr_g1p|sub_parity10a[0,1] ; Stuck at GND due to stuck port clock ;
; DIV:u5|lpm_divide:LPM_DIVIDE_component|lpm_divide_h3t:auto_generated|sign_div_unsign_3li:divider|alt_u_div_tuf:divider|DFFDenominator[0,3] ; Stuck at VCC due to stuck port data_in ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[0..8] ; Stuck at GND due to stuck port data_in ;
; AUDIO_DAC:u12|LRCK_2X_DIV[0..7] ; Lost fanout ;
; AUDIO_DAC:u12|LRCK_4X_DIV[0..6] ; Lost fanout ;
; AUDIO_DAC:u12|LRCK_2X ; Lost fanout ;
; AUDIO_DAC:u12|LRCK_4X ; Lost fanout ;
; AUDIO_DAC:u12|SIN_Cont[0..5] ; Lost fanout ;
; AUDIO_DAC:u12|FLASH_Cont[0..19] ; Lost fanout ;
; I2C_AV_Config:u1|mI2C_DATA[16,17,19,23] ; Stuck at GND due to stuck port data_in ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[16,17,19,23] ; Stuck at GND due to stuck port data_in ;
; Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_bwp|dffe12a[9] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_RD_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:ws_brp|dffe12a[9] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo2|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_bwp|dffe12a[9] ; Lost fanout ;
; Sdram_Control_4Port:u6|Sdram_WR_FIFO:write_fifo1|dcfifo:dcfifo_component|dcfifo_bg02:auto_generated|dffpipe_oe9:rs_brp|dffe12a[9] ; Lost fanout ;
; Shooter:gameLogic|T9Reset ; Merged with Shooter:gameLogic|T10Reset ;
; Shooter:gameLogic|T8Reset ; Merged with Shooter:gameLogic|T10Reset ;
; Shooter:gameLogic|T7Reset ; Merged with Shooter:gameLogic|T10Reset ;
; Shooter:gameLogic|T6Reset ; Merged with Shooter:gameLogic|T10Reset ;
; Shooter:gameLogic|T5Reset ; Merged with Shooter:gameLogic|T10Reset ;
; Shooter:gameLogic|T4Reset ; Merged with Shooter:gameLogic|T10Reset ;
; Shooter:gameLogic|T3Reset ; Merged with Shooter:gameLogic|T10Reset ;
; Shooter:gameLogic|T2Reset ; Merged with Shooter:gameLogic|T10Reset ;
; Shooter:gameLogic|T1Reset ; Merged with Shooter:gameLogic|T10Reset ;
; Sdram_Control_4Port:u6|rWR2_ADDR[0..21] ; Merged with Sdram_Control_4Port:u6|rWR2_ADDR[22] ;
; I2C_AV_Config:u1|mI2C_DATA[20,21] ; Merged with I2C_AV_Config:u1|mI2C_DATA[18] ;
; I2C_AV_Config:u1|I2C_Controller:u0|SD[20,21] ; Merged with I2C_AV_Config:u1|I2C_Controller:u0|SD[18] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[23] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[23] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[22] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[22] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[21] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[21] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[20] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[20] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[19] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[19] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[18] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[18] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[17] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[17] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[16] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[16] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[15] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[15] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[14] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[14] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[13] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[13] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[12] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[12] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[11] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[11] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[10] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[10] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[9] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[9] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[8] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[8] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[7] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[7] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[6] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[6] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[5] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[5] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[4] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[4] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[3] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[3] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[2] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[2] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[1] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[1] ;
; Shooter:gameLogic|Target:T10|stateRateDivide[0] ; Merged with Shooter:gameLogic|Target:T10|directionRateDivide[0] ;
; Shooter:gameLogic|Target:T7|stateRateDivide[23] ; Merged with Shooter:gameLogic|Target:T7|directionRateDivide[23] ;
; Shooter:gameLogic|Target:T7|stateRateDivide[22] ; Merged with Shooter:gameLogic|Target:T7|directionRateDivide[22] ;
; Shooter:gameLogic|Target:T7|stateRateDivide[21] ; Merged with Shooter:gameLogic|Target:T7|directionRateDivide[21] ;
; Shooter:gameLogic|Target:T7|stateRateDivide[20] ; Merged with Shooter:gameLogic|Target:T7|directionRateDivide[20] ;
; Shooter:gameLogic|Target:T7|stateRateDivide[19] ; Merged with Shooter:gameLogic|Target:T7|directionRateDivide[19] ;