We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
1 parent 5640505 commit ac8861aCopy full SHA for ac8861a
README.md
@@ -3,6 +3,6 @@ A library to format/indent/beautify Verilog-AMS source code
3
4
# Demo
5
6
-https://cfgtoolkit.github.io/NVerilogFormatter/
+https://nverilog.github.io/NVerilogFormatter/
7
8

0 commit comments