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| 1 | +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// |
| 2 | +// |
| 3 | +// Licensed under the Apache License, Version 2.0 (the "License"); |
| 4 | +// you may not use this file except in compliance with the License. |
| 5 | +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 |
| 6 | +// |
| 7 | +// Copyright (c) Microsoft Corporation. All rights reserved. |
| 8 | +// Implementation for the MCBSTM32F400 board (STM32F4): Copyright (c) Oberon microsystems, Inc. |
| 9 | +// |
| 10 | +// *** STM32F429IDISCOVERY Block Storage Configuration *** |
| 11 | +// |
| 12 | +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// |
| 13 | + |
| 14 | +#include <tinyhal.h> |
| 15 | + |
| 16 | +#define FLASH_MANUFACTURER_CODE 0x0000 // not used |
| 17 | +#define FLASH_DEVICE_CODE 0x0000 // not used |
| 18 | + |
| 19 | +#define FLASH_BASE_ADDRESS1 0x08000000 // 4x 16KB |
| 20 | +#define FLASH_BLOCK_COUNT1 4 |
| 21 | +#define FLASH_BYTES_PER_BLOCK1 0x04000 |
| 22 | +#define FLASH_BASE_ADDRESS2 0x08010000 // 1x 64KB |
| 23 | +#define FLASH_BLOCK_COUNT2 1 |
| 24 | +#define FLASH_BYTES_PER_BLOCK2 0x10000 |
| 25 | +#define FLASH_BASE_ADDRESS3 0x08020000 // 7x 128KB |
| 26 | +#define FLASH_BLOCK_COUNT3 7 |
| 27 | +#define FLASH_BYTES_PER_BLOCK3 0x20000 |
| 28 | +#define FLASH_BASE_ADDRESS4 0x08100000 // 4x 16KB |
| 29 | +#define FLASH_BLOCK_COUNT4 4 |
| 30 | +#define FLASH_BYTES_PER_BLOCK4 0x04000 |
| 31 | +#define FLASH_BASE_ADDRESS5 0x08110000 // 1x 64KB |
| 32 | +#define FLASH_BLOCK_COUNT5 1 |
| 33 | +#define FLASH_BYTES_PER_BLOCK5 0x10000 |
| 34 | +#define FLASH_BASE_ADDRESS6 0x08120000 // 7x 128KB |
| 35 | +#define FLASH_BLOCK_COUNT6 7 |
| 36 | +#define FLASH_BYTES_PER_BLOCK6 0x20000 |
| 37 | + |
| 38 | +#define FLASH_BYTES_PER_SECTOR 2 |
| 39 | +#define FLASH_BLOCK_ERASE_TYPICAL_TIME_USEC 1000000 // not used |
| 40 | +#define FLASH_SECTOR_WRITE_TYPICAL_TIME_USEC 10 // not used |
| 41 | +#define FLASH_BLOCK_ERASE_MAX_TIME_USEC 4000000 // not used |
| 42 | +#define FLASH_SECTOR_WRITE_MAX_TIME_USEC 100 // not used |
| 43 | +#define FLASH_BLOCK_ERASE_ACTUAL_TIME_USEC 10000 // not used |
| 44 | + |
| 45 | +// EBIU Information |
| 46 | + |
| 47 | +#define STM32F4__CHIP_SELECT 0 |
| 48 | +#define STM32F4__WAIT_STATES 5 // not used |
| 49 | +#define STM32F4__RELEASE_COUNTS 0 |
| 50 | +#define STM32F4__BIT_WIDTH 16 |
| 51 | +#define STM32F4__BASE_ADDRESS 0x08000000 |
| 52 | +#define STM32F4__SIZE_IN_BYTES 0x00100000 |
| 53 | +#define STM32F4__WP_GPIO_PIN GPIO_PIN_NONE |
| 54 | +#define STM32F4__WP_ACTIVE FALSE |
| 55 | + |
| 56 | +// BlockDeviceInformation |
| 57 | + |
| 58 | +#define STM32F4__IS_REMOVABLE FALSE |
| 59 | +#define STM32F4__SUPPORTS_XIP TRUE |
| 60 | +#define STM32F4__WRITE_PROTECTED FALSE |
| 61 | +#define STM32F4__SUPP_COPY_BACK FALSE |
| 62 | +#define STM32F4__NUM_REGIONS 6 |
| 63 | + |
| 64 | + |
| 65 | + |
| 66 | +//--// |
| 67 | + |
| 68 | + |
| 69 | +const BlockRange g_STM32F4_BlockRange1[] = |
| 70 | +{ |
| 71 | + { BlockRange::BLOCKTYPE_BOOTSTRAP , 0, 2 }, // 08000000 bootloader 48k |
| 72 | + { BlockRange::BLOCKTYPE_CONFIG , 3, 3 }, // 0800C000 config 16k |
| 73 | +}; |
| 74 | + |
| 75 | +const BlockRange g_STM32F4_BlockRange2[] = |
| 76 | +{ |
| 77 | + { BlockRange::BLOCKTYPE_CODE , 0, 0 }, // 08010000 CLR 64k |
| 78 | +}; |
| 79 | + |
| 80 | +const BlockRange g_STM32F4_BlockRange3[] = |
| 81 | +{ |
| 82 | + { BlockRange::BLOCKTYPE_CODE , 0, 6 }, // 08020000 CLR 896k |
| 83 | +}; |
| 84 | + |
| 85 | +const BlockRange g_STM32F4_BlockRange4[] = |
| 86 | +{ |
| 87 | + { BlockRange::BLOCKTYPE_DEPLOYMENT, 0, 3 }, // 08100000 deployment 64k |
| 88 | +}; |
| 89 | + |
| 90 | +const BlockRange g_STM32F4_BlockRange5[] = |
| 91 | +{ |
| 92 | + { BlockRange::BLOCKTYPE_DEPLOYMENT, 0, 0 }, // 08110000 deployment 64k |
| 93 | +}; |
| 94 | + |
| 95 | +const BlockRange g_STM32F4_BlockRange6[] = |
| 96 | +{ |
| 97 | + { BlockRange::BLOCKTYPE_DEPLOYMENT, 0, 6 }, // 08120000 deployment 896k |
| 98 | + //{ BlockRange::BLOCKTYPE_UPDATE, 3, 6 }, |
| 99 | +}; |
| 100 | + |
| 101 | + |
| 102 | +const BlockRegionInfo g_STM32F4_BlkRegion[STM32F4__NUM_REGIONS] = |
| 103 | +{ |
| 104 | + { |
| 105 | + FLASH_BASE_ADDRESS1, // ByteAddress Start; // Starting Sector address |
| 106 | + FLASH_BLOCK_COUNT1, // UINT32 NumBlocks; // total number of blocks in this region |
| 107 | + FLASH_BYTES_PER_BLOCK1, // UINT32 BytesPerBlock; // Total number of bytes per block |
| 108 | + ARRAYSIZE_CONST_EXPR(g_STM32F4_BlockRange1), |
| 109 | + g_STM32F4_BlockRange1, |
| 110 | + }, |
| 111 | + |
| 112 | + { |
| 113 | + FLASH_BASE_ADDRESS2, // ByteAddress Start; // Starting Sector address |
| 114 | + FLASH_BLOCK_COUNT2, // UINT32 NumBlocks; // total number of blocks in this region |
| 115 | + FLASH_BYTES_PER_BLOCK2, // UINT32 BytesPerBlock; // Total number of bytes per block |
| 116 | + ARRAYSIZE_CONST_EXPR(g_STM32F4_BlockRange2), |
| 117 | + g_STM32F4_BlockRange2, |
| 118 | + }, |
| 119 | + |
| 120 | + { |
| 121 | + FLASH_BASE_ADDRESS3, // ByteAddress Start; // Starting Sector address |
| 122 | + FLASH_BLOCK_COUNT3, // UINT32 NumBlocks; // total number of blocks in this region |
| 123 | + FLASH_BYTES_PER_BLOCK3, // UINT32 BytesPerBlock; // Total number of bytes per block |
| 124 | + ARRAYSIZE_CONST_EXPR(g_STM32F4_BlockRange3), |
| 125 | + g_STM32F4_BlockRange3, |
| 126 | + }, |
| 127 | + { |
| 128 | + FLASH_BASE_ADDRESS4, // ByteAddress Start; // Starting Sector address |
| 129 | + FLASH_BLOCK_COUNT4, // UINT32 NumBlocks; // total number of blocks in this region |
| 130 | + FLASH_BYTES_PER_BLOCK4, // UINT32 BytesPerBlock; // Total number of bytes per block |
| 131 | + ARRAYSIZE_CONST_EXPR(g_STM32F4_BlockRange4), |
| 132 | + g_STM32F4_BlockRange4, |
| 133 | + }, |
| 134 | + |
| 135 | + { |
| 136 | + FLASH_BASE_ADDRESS5, // ByteAddress Start; // Starting Sector address |
| 137 | + FLASH_BLOCK_COUNT5, // UINT32 NumBlocks; // total number of blocks in this region |
| 138 | + FLASH_BYTES_PER_BLOCK5, // UINT32 BytesPerBlock; // Total number of bytes per block |
| 139 | + ARRAYSIZE_CONST_EXPR(g_STM32F4_BlockRange5), |
| 140 | + g_STM32F4_BlockRange5, |
| 141 | + }, |
| 142 | + |
| 143 | + { |
| 144 | + FLASH_BASE_ADDRESS6, // ByteAddress Start; // Starting Sector address |
| 145 | + FLASH_BLOCK_COUNT6, // UINT32 NumBlocks; // total number of blocks in this region |
| 146 | + FLASH_BYTES_PER_BLOCK6, // UINT32 BytesPerBlock; // Total number of bytes per block |
| 147 | + ARRAYSIZE_CONST_EXPR(g_STM32F4_BlockRange6), |
| 148 | + g_STM32F4_BlockRange6, |
| 149 | + } |
| 150 | +}; |
| 151 | + |
| 152 | +const BlockDeviceInfo g_STM32F4_DeviceInfo= |
| 153 | +{ |
| 154 | + { |
| 155 | + STM32F4__IS_REMOVABLE, // BOOL Removable; |
| 156 | + STM32F4__SUPPORTS_XIP, // BOOL SupportsXIP; |
| 157 | + STM32F4__WRITE_PROTECTED, // BOOL WriteProtected; |
| 158 | + STM32F4__SUPP_COPY_BACK // BOOL SupportsCopyBack |
| 159 | + }, |
| 160 | + FLASH_SECTOR_WRITE_TYPICAL_TIME_USEC, // UINT32 MaxSectorWrite_uSec; |
| 161 | + FLASH_BLOCK_ERASE_ACTUAL_TIME_USEC, // UINT32 MaxBlockErase_uSec; |
| 162 | + FLASH_BYTES_PER_SECTOR, // UINT32 BytesPerSector; |
| 163 | + |
| 164 | + FLASH_MEMORY_Size, // UINT32 Size; |
| 165 | + |
| 166 | + STM32F4__NUM_REGIONS, // UINT32 NumRegions; |
| 167 | + g_STM32F4_BlkRegion, // const BlockRegionInfo* pRegions; |
| 168 | +}; |
| 169 | + |
| 170 | +struct MEMORY_MAPPED_NOR_BLOCK_CONFIG g_STM32F4_BS_Config = |
| 171 | +{ |
| 172 | + { // BLOCK_CONFIG |
| 173 | + { |
| 174 | + STM32F4__WP_GPIO_PIN, // GPIO_PIN Pin; |
| 175 | + STM32F4__WP_ACTIVE, // BOOL ActiveState; |
| 176 | + }, |
| 177 | + |
| 178 | + &g_STM32F4_DeviceInfo, // BlockDeviceinfo |
| 179 | + }, |
| 180 | + |
| 181 | + { // CPU_MEMORY_CONFIG |
| 182 | + STM32F4__CHIP_SELECT, // UINT8 CPU_MEMORY_CONFIG::ChipSelect; |
| 183 | + TRUE, // UINT8 CPU_MEMORY_CONFIG::ReadOnly; |
| 184 | + STM32F4__WAIT_STATES, // UINT32 CPU_MEMORY_CONFIG::WaitStates; |
| 185 | + STM32F4__RELEASE_COUNTS, // UINT32 CPU_MEMORY_CONFIG::ReleaseCounts; |
| 186 | + STM32F4__BIT_WIDTH, // UINT32 CPU_MEMORY_CONFIG::BitWidth; |
| 187 | + STM32F4__BASE_ADDRESS, // UINT32 CPU_MEMORY_CONFIG::BaseAddress; |
| 188 | + STM32F4__SIZE_IN_BYTES, // UINT32 CPU_MEMORY_CONFIG::SizeInBytes; |
| 189 | + 0, // UINT8 CPU_MEMORY_CONFIG::XREADYEnable |
| 190 | + 0, // UINT8 CPU_MEMORY_CONFIG::ByteSignalsForRead |
| 191 | + 0, // UINT8 CPU_MEMORY_CONFIG::ExternalBufferEnable |
| 192 | + }, |
| 193 | + |
| 194 | + 0, // UINT32 ChipProtection; |
| 195 | + FLASH_MANUFACTURER_CODE, // UINT32 ManufacturerCode; |
| 196 | + FLASH_DEVICE_CODE, // UINT32 DeviceCode; |
| 197 | +}; |
| 198 | + |
| 199 | +struct BlockStorageDevice g_STM32F4_BS; |
| 200 | + |
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