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librepcb_sk.ts
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<?xml version="1.0" ?><!DOCTYPE TS><TS version="2.1" language="sk" sourcelanguage="en">
<context>
<name>ArchiveOutputJob</name>
<message>
<location filename="libs/librepcb/core/job/archiveoutputjob.cpp" line="42"/>
<source>Output Archive</source>
<translation>Výstupný archív</translation>
</message>
<message>
<location filename="libs/librepcb/core/job/archiveoutputjob.h" line="71"/>
<source>Archive</source>
<translation>Archív</translation>
</message>
</context>
<context>
<name>AttributeKey</name>
<message>
<location filename="libs/librepcb/core/attribute/attributekey.h" line="55"/>
<source>Invalid attribute key: '%1'</source>
<translation>Nesprávny kľúč atribútu: '%1'</translation>
</message>
</context>
<context>
<name>AttributeType</name>
<message>
<location filename="libs/librepcb/core/attribute/attributetype.cpp" line="77"/>
<source>Unknown unit of attribute type "%1": "%2"</source>
<translation>Neznáma jednotka typu atribútu "%1": "%2"</translation>
</message>
<message>
<location filename="libs/librepcb/core/attribute/attributetype.cpp" line="124"/>
<source>Invalid attribute type: "%1"</source>
<translation>Nesprávny typ atribútu: "%1"</translation>
</message>
</context>
<context>
<name>BGI_FootprintPad</name>
<message>
<location filename="libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_footprintpad.cpp" line="164"/>
<source>Pad:</source>
<translation>Plôška vývodu:</translation>
</message>
<message>
<location filename="libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_footprintpad.cpp" line="170"/>
<source>Signal:</source>
<translation>Signál:</translation>
</message>
<message>
<location filename="libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_footprintpad.cpp" line="176"/>
<source>Net:</source>
<translation>Prepojenie:</translation>
</message>
</context>
<context>
<name>BGI_Via</name>
<message>
<location filename="libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="248"/>
<source>Through-Hole Via</source>
<translation>Štandardný prechod</translation>
</message>
<message>
<location filename="libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="250"/>
<source>Blind Via</source>
<translation>Slepý prechod</translation>
</message>
<message>
<location filename="libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="252"/>
<source>Buried Via</source>
<translation>Pochovaný prechod</translation>
</message>
<message>
<location filename="libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="254"/>
<source>Net: %1</source>
<translation>Prepojenie: %1</translation>
</message>
<message>
<location filename="libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="256"/>
<source>Start Layer: %1</source>
<translation>Začiatočná vrstva: %1</translation>
</message>
<message>
<location filename="libs/librepcb/editor/project/boardeditor/graphicsitems/bgi_via.cpp" line="257"/>
<source>End Layer: %1</source>
<translation>Koncová vrstva: %1</translation>
</message>
</context>
<context>
<name>Board3DOutputJob</name>
<message>
<location filename="libs/librepcb/core/job/board3doutputjob.cpp" line="39"/>
<source>STEP Model</source>
<translation>Model formátu STEP</translation>
</message>
<message>
<location filename="libs/librepcb/core/job/board3doutputjob.h" line="73"/>
<source>3D Model</source>
<translation>3D Model</translation>
</message>
</context>
<context>
<name>BoardDesignRuleCheckMessages</name>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="53"/>
<source>Depending on the capabilities of the PCB manufacturer, this could cause higher costs or even serious troubles during production, leading to a possibly non-functional PCB.</source>
<translation>V závislosti od možností výrobcu DPS, môže toto spôsobiť vyššie náklady alebo dokonca vážne problémy pri výrobe, čo môže viesť aj k prípadnej nefunkčnosti DPS.</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="64"/>
<source>(no net)</source>
<translation>(bez prepojenia)</translation>
</message>
</context>
<context>
<name>BomOutputJob</name>
<message>
<location filename="libs/librepcb/core/job/bomoutputjob.cpp" line="40"/>
<source>Bill of Materials</source>
<translation>Zoznam súčiastok</translation>
</message>
<message>
<location filename="libs/librepcb/core/job/bomoutputjob.h" line="79"/>
<source>Bill Of Materials</source>
<translation>Zoznam súčiastok</translation>
</message>
</context>
<context>
<name>BoundedUnsignedRatio</name>
<message>
<location filename="libs/librepcb/core/types/boundedunsignedratio.cpp" line="108"/>
<source>Minimum value must not be greater than maximum value.</source>
<translation>Minimálna hodnota nesmie byť vyššia ako maximálna hodnota.</translation>
</message>
</context>
<context>
<name>CircuitIdentifier</name>
<message>
<location filename="libs/librepcb/core/types/circuitidentifier.h" line="53"/>
<source>Invalid identifier: '%1'</source>
<translation>Nesprávny identifikátor: '%1'</translation>
</message>
</context>
<context>
<name>CmpSigPinDisplayType</name>
<message>
<location filename="libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="95"/>
<source>None (no text)</source>
<translation>Prázdne (bez textu)</translation>
</message>
<message>
<location filename="libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="101"/>
<source>Symbol pin name</source>
<translation>Názov vývodu sch. značky</translation>
</message>
<message>
<location filename="libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="107"/>
<source>Component signal name</source>
<translation>Názov signálu komponentu</translation>
</message>
<message>
<location filename="libs/librepcb/core/library/cmp/cmpsigpindisplaytype.h" line="113"/>
<source>Schematic net name</source>
<translation>Názov prepojenia v schéme</translation>
</message>
</context>
<context>
<name>CommandLineInterface</name>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="86"/>
<source>Open a project to execute project-related tasks.</source>
<translation>Otvoriť projekt pre vykonanie akcií v ňom.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="89"/>
<source>Open a library to execute library-related tasks.</source>
<translation>Otvoriť knižnicu pre vykonanie akcií v nej.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="92"/>
<source>Open a STEP model to execute STEP-related tasks outside of a library.</source>
<translation>Otvorte STEP model mimo knižnice pre vykonávanie STEP úloh.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="99"/>
<source>LibrePCB Command Line Interface</source>
<translation>Rozhranie príkazového riadka LibrePCB</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="102"/>
<source>Print this message.</source>
<translation>Vytlačiť túto správu.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="105"/>
<source>Displays version information.</source>
<translation>Zobraziť informácie o verzii.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="107"/>
<source>Verbose output.</source>
<translation>Podrobný výstup</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="110"/>
<source>The command to execute (see list below).</source>
<translation>Príkaz na vykonanie (pozri zoznam nižšie).</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="116"/>
<source>Run the electrical rule check, print all non-approved warnings/errors and report failure (exit code = 1) if there are non-approved messages.</source>
<translation>Spustiť kontrolu elektrických pravidiel, zobraziť všetky neschválené upozornenia/chyby a zlyhania (exit code = 1) ak sú neschválené oznámenia.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="121"/>
<source>Run the design rule check, print all non-approved warnings/errors and report failure (exit code = 1) if there are non-approved messages.</source>
<translation>Spustiť kontrolu návrhových pravidiel, zobraziť všetky neschválené upozornenia/chyby a zlyhania (exit code = 1) ak sú neschválené oznámenia.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="126"/>
<source>Override DRC settings by providing a *.lp file containing custom settings. If not set, the settings from the boards will be used instead.</source>
<translation>Prepísať nastavenie DRC, užívateľským nastavením uloženým v *.lp súbore. Ak nie je zadané, použije sa nastaveniez dosky.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="129"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="141"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="152"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="158"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="164"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="181"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="187"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="194"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="200"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="282"/>
<source>file</source>
<translation>súbor</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="132"/>
<source>Run a particular output job. Can be given multiple times to run multiple jobs.</source>
<translation>Spustenie konkrétnej výstupnej úlohy. Dá sa zadať viackrát pre spustenie viacerých úloh.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="134"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="205"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="222"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="234"/>
<source>name</source>
<translation>názov</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="136"/>
<source>Run all existing output jobs.</source>
<translation>Spustenie všetkých jestvujúcich úloh pre generovanie výstupov.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="139"/>
<source>Override output jobs with a *.lp file containing custom jobs. If not set, the jobs from the project will be used instead.</source>
<translation>Prepísať výstupné úlohy nastavením zo súboru *.lp. Ak nie je zadané, použije sa nastavenie z projektu.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="144"/>
<source>Override the output base directory of jobs. If not set, the standard output directory from the project is used.</source>
<translation>Prepísať cieľovú cestu adresára, pre úlohy generovania výstupov. Ak nie je zadané, použije sa nastavenie z projektu.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="146"/>
<source>path</source>
<translation>cesta</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="149"/>
<source>Export schematics to given file(s). Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportovať schematické výkresy do príslušných súborov. Ak súbory už existujú, budú prepísané. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="155"/>
<source>Export generic BOM to given file(s). Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportovať všeobecný zoznam súčiastok do príslušného súboru. Ak súbor už existuje, bude prepísaný. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="161"/>
<source>Export board-specific BOM to given file(s). Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportovať zoznam súčiastok pre konkrétnu dosku do príslušného súboru. Ak súbory už existujú, budú prepísané. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="167"/>
<source>Comma-separated list of additional attributes to be exported to the BOM. Example: "%1"</source>
<translation>Zoznam dodatočných atribútov oddelených čiarkami, ktoré budú exportované do zoznamu súčiastok. Napríklad "%1"</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="170"/>
<source>attributes</source>
<translation>atribúty</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="173"/>
<source>Export PCB fabrication data (Gerber/Excellon) according the fabrication output settings of boards. Existing files will be overwritten.</source>
<translation>Exportovať výrobné dáta (Gerber/Excellon) na základe nastavenia dosky. Ak súbory už existujú, budú prepísané.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="178"/>
<source>Override PCB fabrication output settings by providing a *.lp file containing custom settings. If not set, the settings from the boards will be used instead.</source>
<translation>Prepísať nastavenie generovania výrobných dát dosky, pomocou užívateľského nastavenia z *.lp súboru. Ak nie je zadané, bude použité nastavenie generovania výrobných dát z dosky.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="184"/>
<source>Export pick&place file for automated assembly of the top board side. Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportuje súbor pick&place pre automatické osádzanie súčiastok, pre vrchnú stranu dosky. Jestvujúce súbory budú prepísané. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="190"/>
<source>Export pick&place file for automated assembly of the bottom board side. Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportuje súbor pick&place pre automatické osádzanie súčiastok, pre spodnú stranu dosky. Jestvujúce súbory budú prepísané. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="197"/>
<source>Export netlist file for automated PCB testing. Existing files will be overwritten. Supported file extensions: %1</source>
<translation>Exportuje zoznam prepojení pre automatizované testovanie DPS. Jestvujúce súbory budú prepísané. Podporované prípony súborov: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="202"/>
<source>The name of the board(s) to export. Can be given multiple times. If not set, all boards are exported.</source>
<translation>Názov exportovanej dosky/dosiek. Môže byť zadaných viacej názvov. Ak nie je zadané, všetky dosky budú exportované.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="207"/>
<source>Same as '%1', but allows to specify boards by index instead of by name.</source>
<translation>Rovnako ako '%1', ale umožňuje špecifikovať dosku podľa indexu namiesto názvu.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="210"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="228"/>
<source>index</source>
<translation>index</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="213"/>
<source>Remove all boards not specified with '%1' from the project before executing all the other actions. If '%1' is not passed, all boards will be removed. Pass '%2' to save the modified project to disk.</source>
<translation>Pred vykonaním ostatných akcií, odstráňte z projektu všetky nešpecifkované dosky pomocou '%1'. Ak '%1' nebolo zadané, budú odstránené všetky dosky. Zadaním '%2' bude projekt uložený na disk.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="220"/>
<source>The name of the assembly variant(s) to export. Can be given multiple times. If not set, all assembly variants are exported.</source>
<translation>Názov alternatívneho osadenia DPS na export. Môže byť zadaných viacero názvov. Ak nie je nastavený žiaden, exportujú sa všetky varianty zostavy.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="225"/>
<source>Same as '%1', but allows to specify assembly variants by index instead of by name.</source>
<translation>Rovnako ako '%1', ale umožňuje špecifikovať alternatívne osadenie dosky podľa indexu namiesto názvu.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="231"/>
<source>Move the specified assembly variant to the top before executing all the other actions. Pass '%1' to save the modified project to disk.</source>
<translation>Najskôr presuňte špecifikované alternatívne osadenie nahor pred vykonaním všetkých ostatných akcií. Ak chcete uložiť upravený projekt na disk, zadajte '%1'.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="237"/>
<source>Save project before closing it (useful to upgrade file format).</source>
<translation>Uložiť projekt pred jeho uzavretím (užitočné pre inováciu formátu súboru).</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="240"/>
<source>Fail if the project files are not strictly canonical, i.e. there would be changes when saving the project. Note that this option is not available for *.lppz files.</source>
<translation>Ukončené s chybou, ak projektové súbory nie sú striktne kanonické, t.j. pri ukladaní projektu došlo k zmenám (napr. neboli uložené programom LibrePCB). Upozorňujeme, že táto možnosť nie je k dispozícii pre súbory * .lppz.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="247"/>
<source>Perform the selected action(s) on all elements contained in the opened library.</source>
<translation>Vykonať zvolenú akciu/akcie na všetky položky v otvorenej knižnici.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="251"/>
<source>Run the library element check, print all non-approved messages and report failure (exit code = 1) if there are non-approved messages.</source>
<translation>Spustenie kontroly knižničných prvkov, zobrazenie všetkých neschválených upozornení a oznámenie chýb (exit code = 1) ak jestvujú neschválené oznámenia.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="255"/>
<source>Minify the STEP models of all packages. Only works in conjunction with '--all'. Pass '--save' to write the minified files to disk.</source>
<translation>Minify the STEP models of all packages. Only works in conjunction with '--all'. Pass '--save' to write the minified files to disk.
Minimalizuje všetky STEP modely. Funguje iba v spojení s '--all'. Ak chcete zapísať minimalizované súbory na disk, zadajte „--save“.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="259"/>
<source>Save library (and contained elements if '--all' is given) before closing them (useful to upgrade file format).</source>
<translation>Uložiť knižnicu (a obsahujúce položky ak '--all' bol zadaný) pred jej uzavretím (užitočné pre inováciu formátu knižnice).</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="263"/>
<source>Fail if the opened files are not strictly canonical, i.e. there would be changes when saving the library elements.</source>
<translation>Ukončené s chybou, ak otvorené súbory nie sú striktne kanonické, t.j. pri ukladaní prvkov knižnice došlo k zmenám (napr. neboli uložené programom LibrePCB).</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="269"/>
<source>Minify the STEP model before validating it. Use in conjunction with '%1' to save the output of the operation.</source>
<translation>Minimalizujte STEP model pred jeho použitím. Použite v spolupráci s '%1' pre uloženie výstupu operácie.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="274"/>
<source>Tesselate the loaded STEP model to check if LibrePCB is able to render it. Reports failure (exit code = 1) if no content is detected.</source>
<translation>Rozdeľte načítaný STEP model a skontrolujte, či ho LibrePCB dokáže vykresliť. Ak sa nezistí žiadny obsah, hlásené je zlyhanie (kód ukončenia = 1).</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="279"/>
<source>Write the (modified) STEP file to this output location (may be equal to the opened file path). Only makes sense in conjunction with '%1'.</source>
<translation>Zapíšte (upravený) súbor STEP do tohto výstupného umiestnenia (môže sa rovnať otvorenej ceste k súboru). Má zmysel iba v spojení s '%1'.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="286"/>
<source>Commands:</source>
<translation>Príkazy:</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="290"/>
<source>List command-specific options:</source>
<translation>Vypísať špecifické možnosti pre príkazy:</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="293"/>
<source>Help:</source>
<translation>Pomocník:</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="307"/>
<source>Path to project file (*.lpp[z]).</source>
<translation>Cesta k súboru projektu (*.lpp[z]).</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="337"/>
<source>Path to library directory (*.lplib).</source>
<translation>Cesta do adresára s knižnicou (*.lplib).</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="348"/>
<source>Path to the STEP file (%1).</source>
<translation>Cesta k súboru STEP (%1).</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="354"/>
<source>Unknown command '%1'.</source>
<translation>Neznámy príkaz '%1'.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="411"/>
<source>Missing arguments:</source>
<translation>Chýbajúce argumenty:</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="417"/>
<source>Unknown arguments:</source>
<translation>Neznáme argumenty:</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="471"/>
<source>SUCCESS</source>
<translation>ÚSPEŠNÉ</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="474"/>
<source>Finished with errors!</source>
<translation>Ukončené s chybami!</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="503"/>
<source>Open project '%1'...</source>
<translation>Otváranie projektu '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="525"/>
<source>Attention: Project has been upgraded to a newer file format!</source>
<translation>Upozornenie: Formát súboru projektu bol inovovaný na najnovší!</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="546"/>
<source>Set default assembly variant to '%1'...</source>
<translation>Nastaviť predvolené alternatívne osadenie na '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="551"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="565"/>
<source>ERROR: No assembly variant with the name '%1' found.</source>
<translation>CHYBA: Alternatívne osadenie s názvom '%1' nebolo nájdené.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="580"/>
<source>ERROR: Assembly variant index '%1' is invalid.</source>
<translation>CHYBA: Alternatívne osadenie s indexom '%1' je neplatné.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="602"/>
<source>ERROR: No board with the name '%1' found.</source>
<translation>CHYBA: Doska s názvom '%1' neexistuje.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="615"/>
<source>ERROR: Board index '%1' is invalid.</source>
<translation>CHYBA: Index dosky '%1' nie je platný.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="623"/>
<source>Remove other boards...</source>
<translation>Odstrániť iné dosky....</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="652"/>
<source>Check for non-canonical files...</source>
<translation>Kontrola na ne-kanonické súbory...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="655"/>
<source>ERROR: The option '--strict' is not available for *.lppz files!</source>
<translation>CHYBA: Možnosť '--strict' nie je dostupná pre súbory typu *.lppz !</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="678"/>
<source>Run ERC...</source>
<translation>Spustené ERC...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="684"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="725"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1271"/>
<source>Approved messages: %1</source>
<translation>Schválené oznámenia: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="685"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="727"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1273"/>
<source>Non-approved messages: %1</source>
<translation>Neschválené oznámenia: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="694"/>
<source>Run DRC...</source>
<translation>Spustené DRC...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="706"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="911"/>
<source>ERROR: Failed to load custom settings: %1</source>
<translation>CHYBA: Nepodarilo sa načítať užívateľské nastavenie: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="712"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="917"/>
<source>Board '%1':</source>
<translation>Doska '%1':</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="747"/>
<source>ERROR: Failed to load custom output jobs: %1</source>
<translation>CHYBA: Neúspešné načítanie užívateľských úloh generovania výstupov: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="763"/>
<source>ERROR: No output job with the name '%1' found.</source>
<translation>CHYBA: Úloha generovania výstupov s názvom '%1' nebola nájdená.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="774"/>
<source>Run output job '%1'...</source>
<translation>Spustená úloha generovania výstupov '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="793"/>
<source>ERROR:</source>
<translation>CHYBA:</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="801"/>
<source>Export schematics to '%1'...</source>
<translation>Exportovanie listov schém do '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="825"/>
<source>ERROR</source>
<translation>CHYBA</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="854"/>
<source>Export board-specific BOM to '%1'...</source>
<translation>Exportovanie zoznamu súčiastok dosky do '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="857"/>
<source>Export generic BOM to '%1'...</source>
<translation>Exportovanie všeobecný zoznam súčiastok do '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="887"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="978"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1005"/>
<source>ERROR: Unknown extension '%1'.</source>
<translation>Chyba: neznáma prípona '%1'.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="897"/>
<source>Export PCB fabrication data...</source>
<translation>Exportovanie výrobných dát DPS...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="940"/>
<source>top</source>
<translation>vrchná</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="944"/>
<source>bottom</source>
<translation>spodná</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="948"/>
<source>Export %1 assembly data to '%2'...</source>
<translation>Exportovanie dát osadenia %1 do '%2'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="988"/>
<source>Export netlist to '%1'...</source>
<translation>Exportovanie zoznamu prepojení do '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1013"/>
<source>Save project...</source>
<translation>Ukladanie projektu....</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1034"/>
<source>ERROR: The file '%1' was written multiple times!</source>
<translation>CHYBA: Súbor '%1' bol viac krát prepísaný!</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1039"/>
<source>NOTE: To avoid writing files multiple times, make sure to pass unique filepaths to all export functions. For board output files, you could either add the placeholder '%1' to the path or specify the boards to export with the '%2' argument.</source>
<translation>POZNÁMKA: Aby ste sa vyhli viacnásobnému zápisu do súboru, skontrolujte jedinečnosť cesty súborov pri exportovaní. Pre výstupy dosky, môžete použiť zástupný symbol '%1' ako cestu, alebo zadajte exportovanú dosku s '%2' argumentom.</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1050"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1190"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1368"/>
<source>ERROR: %1</source>
<translation>CHYBA: %1</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1063"/>
<source>Open library '%1'...</source>
<translation>Otváranie knižnice '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1078"/>
<source>Process %1 component categories...</source>
<translation>Spracovávanie %1 kategórie komponentov...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1081"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1100"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1119"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1138"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1157"/>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1176"/>
<source>Open '%1'...</source>
<translation>Otváranie '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1097"/>
<source>Process %1 package categories...</source>
<translation>Spracovávanie %1 kategórie púzdier...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1116"/>
<source>Process %1 symbols...</source>
<translation>Spracovávanie %1 sch. značky...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1135"/>
<source>Process %1 packages...</source>
<translation>Spracovávanie %1 puzdra...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1154"/>
<source>Process %1 components...</source>
<translation>Spracovávanie %1 komponenty...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1173"/>
<source>Process %1 devices...</source>
<translation>Spracovávanie %1 súčiastky...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1221"/>
<source>Minify STEP model '%1'...</source>
<translation>Minimalizácia STEP modelu '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1227"/>
<source> - Minified '%1' from %2 to %3 bytes</source>
<translation> - Minimalizovaný '%1' z %2 na %3 bytes</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1246"/>
<source>Check '%1' for non-canonical files...</source>
<translation>Kontrolovanie '%1' na ne-kanonické súbory...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1264"/>
<source>Check '%1' for non-approved messages...</source>
<translation>Kontrolovanie '%1' na neschválené oznámenia...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1284"/>
<source>Save '%1'...</source>
<translation>Ukladanie '%1'...</translation>
</message>
<message>
<location filename="apps/librepcb-cli/commandlineinterface.cpp" line="1420"/>
<source>This application version is UNSTABLE! Option '%1' is disabled to avoid breaking projects or libraries. Please use a stable release instead.</source>
<translation>Táto verzia aplikácie je NESTABILNÁ! Možnosť '%1' je deaktivovaná, aby nedošlo k poškodeniu projektov alebo knižníc. Namiesto toho použite prosím stabilnú verziu.</translation>
</message>
</context>
<context>
<name>ComponentPrefix</name>
<message>
<location filename="libs/librepcb/core/library/cmp/componentprefix.h" line="56"/>
<source>Invalid component prefix: '%1'</source>
<translation>Neplatný prefix komponentu: '%1'</translation>
</message>
</context>
<context>
<name>ComponentSymbolVariantItemSuffix</name>
<message>
<location filename="libs/librepcb/core/library/cmp/componentsymbolvariantitemsuffix.h" line="57"/>
<source>Invalid component symbol suffix: '%1'</source>
<translation>Neplatný sufix sch. značky komponentu: '%1'</translation>
</message>
</context>
<context>
<name>CopyOutputJob</name>
<message>
<location filename="libs/librepcb/core/job/copyoutputjob.cpp" line="39"/>
<source>Custom File</source>
<translation>Užívateľský súbor</translation>
</message>
<message>
<location filename="libs/librepcb/core/job/copyoutputjob.h" line="78"/>
<source>File Copy</source>
<translation>Kópia súboru</translation>
</message>
</context>
<context>
<name>DesktopIntegration</name>
<message>
<location filename="libs/librepcb/editor/workspace/desktopintegration.cpp" line="130"/>
<source>To avoid troubles, only proceed if there are no other (installed) LibrePCB applications on this computer.</source>
<translation>Aby ste sa vyhli problémom, pokračujte iba vtedy, ak na tomto počítači nie sú žiadne iné (nainštalované) aplikácie LibrePCB.</translation>
</message>
<message>
<location filename="libs/librepcb/editor/workspace/desktopintegration.cpp" line="143"/>
<source>Install Desktop Integration</source>
<translation>Inštalovať integráciu do pracovnej plochy</translation>
</message>
<message>
<location filename="libs/librepcb/editor/workspace/desktopintegration.cpp" line="144"/>
<source>This installs the following files to register the executable <i>%1</i>:</source>
<translation>Týmto sa nainštalujú a budú zaregistrované ako spúšťacie, nasledujúce súbory <i>%1</i>:</translation>
</message>
<message>
<location filename="libs/librepcb/editor/workspace/desktopintegration.cpp" line="152"/>
<source>Uninstall Desktop Integration</source>
<translation>Odinštalovať integráciu z pracovnej plochy</translation>
</message>
<message>
<location filename="libs/librepcb/editor/workspace/desktopintegration.cpp" line="153"/>
<source>This removes the following files:</source>
<translation>Toto spôsobí odstránenie nasledujúcich súborov:</translation>
</message>
<message>
<location filename="libs/librepcb/editor/workspace/desktopintegration.cpp" line="176"/>
<source>Error</source>
<translation>Chyba</translation>
</message>
<message>
<location filename="libs/librepcb/editor/workspace/desktopintegration.cpp" line="259"/>
<source>Failed to run '%1'.
Please make sure this tool is available in PATH.</source>
<translation>Chyba pri spúšťaní '%1'.
Prosím skontrolujte či je tento nástroj dostupný cez premennú PATH.</translation>
</message>
</context>
<context>
<name>DirectoryLock</name>
<message>
<location filename="libs/librepcb/core/fileio/directorylock.cpp" line="79"/>
<location filename="libs/librepcb/core/fileio/directorylock.cpp" line="191"/>
<source>The directory "%1" does not exist.</source>
<translation>Adresár "%1" neexistuje.</translation>
</message>
<message>
<location filename="libs/librepcb/core/fileio/directorylock.cpp" line="97"/>
<source>The lock file "%1" has too few lines.</source>
<translation>Súbor "%1" obsahuje príliš málo riadkov.</translation>
</message>
<message>
<location filename="libs/librepcb/core/fileio/directorylock.cpp" line="170"/>
<source>Could not lock the directory "%1" because it is already locked by "%2". Close any application accessing this directory and try again.</source>
<translation>Adresár "%1" sa nedá uzamknúť, pretože už je uzamknutý pomocou "%2". Zatvorte aplikáciu používajúcu tento adresár a skúste to znova.</translation>
</message>
</context>
<context>
<name>DrcMsgCopperBoardClearanceViolation</name>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="625"/>
<source>Clearance via ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Vzdialenosť prechodu ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="628"/>
<source>The clearance between a via and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi prechodom a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="632"/>
<source>Check the DRC settings and move the via away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte prechod ďalej od obrysu dosky.</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="647"/>
<source>Clearance trace ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Odsadenie spoja ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="650"/>
<source>The clearance between a trace and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi spojom a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="654"/>
<source>Check the DRC settings and move the trace away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte spoj ďalej od obrysu dosky.</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="670"/>
<source>Clearance pad ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Vzdialenosť plôšky vývodu ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="673"/>
<source>The clearance between a footprint pad and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi plôškou vývodu a obrysu dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="677"/>
<source>Check the DRC settings and move the device away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte súčiastku ďalej od obrysu dosky.</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="692"/>
<source>Clearance plane ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Vzdialenosť vyplnenej plochy ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="695"/>
<source>The clearance between a plane and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi vyplnenou plochou a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="699"/>
<source>Check the DRC settings and increase the configured plane clearance if needed.</source>
<translation>Skontrolujte nastavenie DRC a zväčšite vzdialenosť vyplnenej plochy.</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="713"/>
<source>Clearance copper polygon ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Vzdialenosť polygónu ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="716"/>
<source>The clearance between a polygon and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi polygónom a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="719"/>
<source>Check the DRC settings and move the polygon away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte polygón ďalej od obrysu dosky.</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="736"/>
<source>Clearance copper circle ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Vzdialenosť vodivej kružnice ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="739"/>
<source>The clearance between a circle and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi kružnicou a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="742"/>
<source>Check the DRC settings and move the circle away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte kružnicu ďalej od obrysu dosky.</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="758"/>
<source>Clearance copper text ↔ board outline < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Vzdialenosť textu ↔ obrysu dosky < %1 %2</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="761"/>
<source>The clearance between a stroke text and the board outline is smaller than the board outline clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi textom a obrysom dosky je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="765"/>
<source>Check the DRC settings and move the stroke text away from the board outline if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte text ďalej od obrysu dosky.</translation>
</message>
</context>
<context>
<name>DrcMsgCopperCopperClearanceViolation</name>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="503"/>
<source>trace</source>
<translation>spoj</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="505"/>
<source>via</source>
<translation>prechod</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="507"/>
<source>plane</source>
<translation>vyplnená plocha</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="509"/>
<source>polygon</source>
<translation>polygón</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="511"/>
<source>circle</source>
<translation>oblúk</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="513"/>
<source>text</source>
<translation>text</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="582"/>
<source>Clearance on %1: %2 ↔ %3 < %4 %5</source>
<comment>Placeholders: Layer name, object name, object name, Clearance value, unit</comment>
<translation>Vzdialenosť odsadenia na %1: %2 ↔ %3 < %4 %5</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="587"/>
<source>The clearance between two copper objects of different nets is smaller than the minimum copper clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi dvoma vodivým objektami rozdielnych prepojení je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="591"/>
<source>Check the DRC settings and move the objects to increase their clearance if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte objekty tak, aby sa zväčšila vzdialenosť medzi nimi.</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="613"/>
<source>%1 layers</source>
<comment>Placeholder is a number > 1.</comment>
<translation>%1 vrstiev</translation>
</message>
</context>
<context>
<name>DrcMsgCopperHoleClearanceViolation</name>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="787"/>
<source>Clearance copper ↔ hole < %1 %2</source>
<comment>Placeholders: Clearance value, unit</comment>
<translation>Vzdialenosť vodivého prvku ↔ otvoru < %1 %2</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="790"/>
<source>The clearance between a non-plated hole and copper objects is smaller than the hole clearance configured in the DRC settings.</source>
<translation>Vzdialenosť medzi nepokovovaným otvorom a vodivým prvkom je menšia ako je nastavená v návrhových pravidlách (DRC).</translation>
</message>
<message>
<location filename="libs/librepcb/core/project/board/drc/boarddesignrulecheckmessages.cpp" line="793"/>
<source>Check the DRC settings and move the copper objects away from the hole if needed.</source>
<translation>Skontrolujte nastavenie DRC a presuňte vodivý objekt ďalej od otvoru.</translation>
</message>
</context>
<context>
<name>DrcMsgCopperInKeepoutZone</name>
<message>