ac97/ac97-1.2-r1.core

@@ -0,0 +1,56 @@
+CAPI=2:
+description: OpenCores AC97 Controller core
+filesets:
+  rtl_files:
+    file_type: verilogSource
+    files:
+    - rtl/verilog/ac97_defines.v:
+        is_include_file: true
+    - rtl/verilog/ac97_cra.v
+    - rtl/verilog/ac97_dma_if.v
+    - rtl/verilog/ac97_dma_req.v
+    - rtl/verilog/ac97_fifo_ctrl.v
+    - rtl/verilog/ac97_in_fifo.v
+    - rtl/verilog/ac97_int.v
+    - rtl/verilog/ac97_out_fifo.v
+    - rtl/verilog/ac97_prc.v
+    - rtl/verilog/ac97_rf.v
+    - rtl/verilog/ac97_rst.v
+    - rtl/verilog/ac97_sin.v
+    - rtl/verilog/ac97_soc.v
+    - rtl/verilog/ac97_sout.v
+    - rtl/verilog/ac97_top.v
+    - rtl/verilog/ac97_wb_if.v
+  tb_files:
+    file_type: verilogSource
+    files:
+    - bench/verilog/ac97_codec_sin.v
+    - bench/verilog/ac97_codec_sout.v
+    - bench/verilog/ac97_codec_top.v
+    - bench/verilog/test_bench_top.v
+    - bench/verilog/tests.v:
+        is_include_file: true
+    - bench/verilog/wb_mast_model.v
+    - bench/verilog/wb_model_defines.v:
+        is_include_file: true
+name: ::ac97:1.2-r1
+provider:
+  name: github
+  patches: []
+  repo: ac97
+  user: freecores
+  version: a47e1fd5a2c5b9eb962b4790ab31873772b457e5
+targets:
+  default:
+    filesets:
+    - rtl_files
+    - tb_files
+  sim:
+    default_tool: icarus
+    filesets:
+    - rtl_files
+    - tb_files
+    toplevel: test
+  synth:
+    filesets:
+    - rtl_files

altera_virtual_jtag/altera_virtual_jtag-1.0-r1.core

@@ -0,0 +1,16 @@
+CAPI=2:
+name: ::altera_virtual_jtag:1.0-r1
+description: Advanced Debug System wrapper for altera virtual jtag
+
+filesets:
+  rtl_files:
+    files: [altera_virtual_jtag.v : {file_type: verilogSource}]
+
+targets:
+  default:
+    filesets: [rtl_files]
+
+provider:
+  name: url
+  filetype: simple
+  url: https://raw.githubusercontent.com/fusesoc/tiny-cores/2353a67ee0e51e3d458eb7bc71a8e1d06438a31c/altera_virtual_jtag/altera_virtual_jtag.v

cdc_utils/cdc_utils-0.1-r1.core

@@ -0,0 +1,22 @@
+CAPI=2:
+name: ::cdc_utils:0.1-r1
+description: Verilog CDC implementations
+
+filesets:
+  rtl:
+    files:
+      - rtl/verilog/sync2_pgen.v
+      - rtl/verilog/cc561.v
+    file_type: verilogSource
+  sdc:
+    files: [data/cdc_utils.sdc : {file_type : SDC}]
+
+targets:
+  default:
+    filesets: [rtl, "tool_quartus? (sdc)"]
+
+provider:
+  name: github
+  user: fusesoc
+  repo: cdc_utils
+  version: v0.1

chipsalliance.org/swerv_el2.core

@@ -0,0 +1,104 @@
+CAPI=2:
+
+name : chipsalliance.org:cores:SweRV_EL2:1.2
+description : SweRV EL2 RISC-V Core
+
+filesets:
+  rtl:
+    files:
+      - design/include/el2_def.sv
+      - design/lib/el2_lib.sv
+      - design/lib/beh_lib.sv
+      - design/el2_mem.sv
+      - design/el2_pic_ctrl.sv
+      - design/el2_dma_ctrl.sv
+      - design/ifu/el2_ifu_aln_ctl.sv
+      - design/ifu/el2_ifu_compress_ctl.sv
+      - design/ifu/el2_ifu_ifc_ctl.sv
+      - design/ifu/el2_ifu_bp_ctl.sv
+      - design/ifu/el2_ifu_ic_mem.sv
+      - design/ifu/el2_ifu_mem_ctl.sv
+      - design/ifu/el2_ifu_iccm_mem.sv
+      - design/ifu/el2_ifu.sv
+      - design/dec/el2_dec_decode_ctl.sv
+      - design/dec/el2_dec_gpr_ctl.sv
+      - design/dec/el2_dec_ib_ctl.sv
+      - design/dec/el2_dec_tlu_ctl.sv
+      - design/dec/el2_dec_trigger.sv
+      - design/dec/el2_dec.sv
+      - design/exu/el2_exu_alu_ctl.sv
+      - design/exu/el2_exu_mul_ctl.sv
+      - design/exu/el2_exu_div_ctl.sv
+      - design/exu/el2_exu.sv
+      - design/lsu/el2_lsu.sv
+      - design/lsu/el2_lsu_bus_buffer.sv
+      - design/lsu/el2_lsu_clkdomain.sv
+      - design/lsu/el2_lsu_addrcheck.sv
+      - design/lsu/el2_lsu_lsc_ctl.sv
+      - design/lsu/el2_lsu_stbuf.sv
+      - design/lsu/el2_lsu_bus_intf.sv
+      - design/lsu/el2_lsu_ecc.sv
+      - design/lsu/el2_lsu_dccm_mem.sv
+      - design/lsu/el2_lsu_dccm_ctl.sv
+      - design/lsu/el2_lsu_trigger.sv
+      - design/dbg/el2_dbg.sv
+      - design/dmi/dmi_wrapper.v
+      - design/dmi/dmi_jtag_to_core_sync.v
+      - design/dmi/rvjtag_tap.v
+      - design/lib/mem_lib.sv
+      - design/el2_swerv.sv
+      - design/el2_swerv_wrapper.sv
+    file_type : systemVerilogSource
+
+  vivado_tcl: {files: [tools/vivado.tcl : {file_type : tclSource}]}
+
+targets:
+  default:
+    filesets :
+      - rtl
+      - "tool_vivado ? (vivado_tcl)"
+  lint:
+    default_tool: verilator
+    filesets : [rtl]
+    generate : [swerv_default_config]
+    tools:
+      verilator :
+        mode : lint-only
+    toplevel : el2_swerv_wrapper
+
+  synth:
+    default_tool : vivado
+    filesets : [rtl, vivado_tcl]
+    generate : [swerv_default_config]
+    parameters : [RV_FPGA_OPTIMIZE]
+    tools:
+      vivado:
+        part : xc7a100tcsg324-1
+        pnr  : none
+    toplevel : el2_swerv_wrapper
+
+generate:
+  swerv_default_config:
+    generator: swerv_el2_config
+    position : first
+    parameters:
+      args : [-unset=assert_on]
+
+generators:
+  swerv_el2_config:
+    interpreter: python3
+    command: configs/swerv_config_gen.py
+    description : Create a SweRV EL2 configuration. Note! Only supports the default config
+
+parameters:
+  RV_FPGA_OPTIMIZE:
+    datatype : bool
+    default : true
+    description : Minimize clock gating to map better to FPGAs
+    paramtype : vlogdefine
+
+provider:
+  name    : github
+  user    : chipsalliance
+  repo    : Cores-SweRV-EL2
+  version : 4c5674ca354056b27e88cb7821ab0aa36f4102e2