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simple_spi/simple_spi-1.6.1.core
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+CAPI=2:
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+
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+name : ::simple_spi:1.6.1
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+description : OpenCores SPI Core
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+filesets:
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+ rtl:
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+ files:
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+ - rtl/verilog/fifo4.v
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+ - rtl/verilog/simple_spi_top.v
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+ file_type : verilogSource
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+ tb:
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+ - bench/verilog/tst_bench_top.v
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+ - bench/verilog/spi_slave_model.v
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+ - bench/verilog/wb_master_model.v
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+ depend: [vlog_tb_utils]
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+targets:
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+ default:
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+ filesets: [rtl]
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+ lint:
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+ default_tool : verilator
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+ filesets : [rtl]
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+ tools: {verilator : {mode : lint-only}}
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+ toplevel : simple_spi
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+ sim:
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+ default_tool: icarus
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+ filesets: [rtl,tb]
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+ toplevel: tst_bench_top
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+provider:
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+ name : github
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+ user : olofk
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+ repo : simple_spi
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+ version : v1.6.1
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