adv_debug_sys-3.1.0: Mark testbench files as private

olofk · olofk · commit afa5f2e4c055 · 2017-10-08T11:13:25.000+02:00
diff --git a/adv_debug_sys/adv_debug_sys-3.1.0.core b/adv_debug_sys/adv_debug_sys-3.1.0.core
@@ -28,6 +28,7 @@ files =
  Hardware/jtag/tap/rtl/verilog/tap_top.v
  Hardware/adv_dbg_if/bench/jtag_serial_port/adv_dbg_jsp_tb.v
 file_type=verilogSource
+scope=private
 usage = sim
 
 [simulator]
