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| 1 | +CAPI=2: |
| 2 | +name : ::wb_sdram_ctrl:0-r4 |
| 3 | +filesets: |
| 4 | + rtl: |
| 5 | + files: |
| 6 | + - rtl/verilog/wb_port_arbiter.v |
| 7 | + - rtl/verilog/bufram.v |
| 8 | + - rtl/verilog/dpram_altera.v |
| 9 | + - rtl/verilog/dpram_ecp5.v |
| 10 | + - rtl/verilog/dpram_generic.v |
| 11 | + - rtl/verilog/dual_clock_fifo.v |
| 12 | + - rtl/verilog/sdram_ctrl.v |
| 13 | + - rtl/verilog/wb_port.v |
| 14 | + - rtl/verilog/wb_sdram_ctrl.v |
| 15 | + file_type : verilogSource |
| 16 | + |
| 17 | + tb: |
| 18 | + files : [bench/wb_sdram_ctrl_tb.v] |
| 19 | + file_type : verilogSource |
| 20 | + depend: |
| 21 | + [mt48lc16m16a2, ">=vlog_tb_utils-1.0", ">=wb_bfm-1.0"] |
| 22 | + |
| 23 | +parameters: |
| 24 | + transactions: |
| 25 | + datatype : int |
| 26 | + description : Number of wishbone transactions to run in test bench |
| 27 | + paramtype : plusarg |
| 28 | + |
| 29 | + subtransactions: |
| 30 | + datatype : int |
| 31 | + description : Number of wishbone transactions to run in test bench |
| 32 | + paramtype : plusarg |
| 33 | + |
| 34 | + seed: |
| 35 | + datatype : int |
| 36 | + description : Initial random seed |
| 37 | + paramtype : plusarg |
| 38 | + |
| 39 | + technology: |
| 40 | + datatype : str |
| 41 | + description : Select DPRAM implementation. Legal values are ALTERA, ECP5 or GENERIC (default) |
| 42 | + paramtype : vlogparam |
| 43 | + |
| 44 | + USE_LATTICE_GSR_PUR: |
| 45 | + datatype: bool |
| 46 | + paramtype : vlogdefine |
| 47 | +targets: |
| 48 | + default: |
| 49 | + filesets: [rtl] |
| 50 | + sim: &sim |
| 51 | + default_tool : icarus |
| 52 | + filesets : [rtl, tb] |
| 53 | + parameters : [transactions, subtransactions, seed, technology] |
| 54 | + tools: |
| 55 | + modelsim: |
| 56 | + vlog_options : [-timescale=1ns/1ps] |
| 57 | + vsim_options : [-t, 1ps] |
| 58 | + toplevel : [wb_sdram_ctrl_tb] |
| 59 | + sim_altsyncram: |
| 60 | + <<: *sim |
| 61 | + parameters : [transactions, subtransactions, seed, technology=ALTERA] |
| 62 | + tools: |
| 63 | + icarus: |
| 64 | + iverilog_options : [-l, $(QUARTUS_ROOTDIR)/eda/sim_lib/altera_mf.v] |
| 65 | + modelsim: |
| 66 | + vlog_options : [-timescale=1ns/1ps] |
| 67 | + vsim_options : [-t, 1ps, -L, altera_mf_ver] |
| 68 | + sim_ecp5: |
| 69 | + <<: *sim |
| 70 | + parameters : [transactions, subtransactions, seed, technology=ECP5, USE_LATTICE_GSR_PUR=true] |
| 71 | + tools: |
| 72 | + icarus: |
| 73 | + iverilog_options : [-y, $(FOUNDRY)/verilog/data/ecp5u] |
| 74 | + |
| 75 | + |
| 76 | +provider: |
| 77 | + name : github |
| 78 | + user : olofk |
| 79 | + repo : wb_sdram_ctrl |
| 80 | + version : 26eb18d5e652333650cfe1d8fee469c8695f703a |
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