Add pulp-platform.org::common_cells:1.16.4

Author: olofk

pulp-platform.org/common_cells-1.16.4.core

@@ -0,0 +1,99 @@
+CAPI=2:
+
+name : pulp-platform.org::common_cells:1.16.4
+
+filesets:
+  includes:
+    files:
+      #Ugly workaround
+      - include/dummy : {is_include_file : true}
+
+      - include/common_cells/registers.svh : {file_type : user}
+    file_type : systemVerilogSource
+
+  rtl:
+    files:
+      # Source files grouped in levels. Files in level 0 have no dependencies on files in this package.
+      # Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0,
+      # etc. Files within a level are ordered alphabetically.
+      # Level 0
+      - src/addr_decode.sv
+      - src/cdc_2phase.sv
+      - src/cf_math_pkg.sv
+      - src/clk_div.sv
+      - src/delta_counter.sv
+      - src/edge_propagator_tx.sv
+      - src/exp_backoff.sv
+      - src/fifo_v3.sv
+      - src/graycode.sv
+      - src/lfsr.sv
+      - src/lfsr_16bit.sv
+      - src/lfsr_8bit.sv
+      - src/lzc.sv
+      - src/mv_filter.sv
+      - src/onehot_to_bin.sv
+      - src/plru_tree.sv
+      - src/popcount.sv
+      - src/rr_arb_tree.sv
+      - src/rstgen_bypass.sv
+      - src/serial_deglitch.sv
+      - src/shift_reg.sv
+      - src/spill_register.sv
+      - src/stream_demux.sv
+      - src/stream_filter.sv
+      - src/stream_fork.sv
+      - src/stream_mux.sv
+      - src/sub_per_hash.sv
+      - src/sync.sv
+      - src/sync_wedge.sv
+      - src/unread.sv
+      # Level 1
+      - src/cb_filter.sv
+      - src/cdc_fifo_2phase.sv
+      - src/cdc_fifo_gray.sv
+      - src/counter.sv
+      - src/edge_detect.sv
+      - src/id_queue.sv
+      - src/max_counter.sv
+      - src/rstgen.sv
+      - src/stream_delay.sv
+      # Level 2
+      - src/fall_through_register.sv
+      - src/stream_arbiter_flushable.sv
+      - src/stream_register.sv
+      # Level 3
+      - src/stream_arbiter.sv
+    file_type : systemVerilogSource
+
+  deprecated:
+    files:
+      # Deprecated modules
+      # Level 0
+      - src/deprecated/clock_divider_counter.sv
+      - src/deprecated/find_first_one.sv
+      - src/deprecated/generic_LFSR_8bit.sv
+      - src/deprecated/generic_fifo.sv
+      - src/deprecated/prioarbiter.sv
+      - src/deprecated/pulp_sync.sv
+      - src/deprecated/pulp_sync_wedge.sv
+      - src/deprecated/rrarbiter.sv
+      # Level 1
+      - src/deprecated/clock_divider.sv
+      - src/deprecated/fifo_v2.sv
+      # Level 2
+      - src/deprecated/fifo_v1.sv
+    
+      # Depend on deprecated modules
+      - src/edge_propagator.sv
+      - src/edge_propagator_rx.sv
+    file_type : systemVerilogSource
+
+targets:
+  default:
+    filesets : [includes, rtl, deprecated]
+
+provider:
+  name : github
+  user : pulp-platform
+  repo : common_cells
+  version : v1.16.4