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build.tcl
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#*****************************************************************************************
# Vivado (TM) v2017.3 (64-bit)
#
# build.tcl: Tcl script for re-creating project 'audioOutAXI'
#
# Generated by Vivado on Mon Jun 18 20:53:55 -0700 2018
# IP Build 2016188 on Wed Oct 4 21:52:56 MDT 2017
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (build.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# "D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/imports/myNote.vhd"
# "D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/counter.vhd"
# "D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/debouncer.vhd"
# "D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/dflipflop.vhd"
# "D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/genericDebouncer.vhdl"
# "D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/beatDetector.vhd"
# "D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/audioMixing.vhd"
# "D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/bd/audioTest/hdl/audioTest_wrapper.vhd"
# "D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/debouncer5.vhd"
# "D:/github/audioOutAXI/audioOutAXI.srcs/constrs_1/imports/ZedBoardAudio-master/constraintAudio.xdc"
#
# 3. The following remote source files that were added to the original project:-
#
# <none>
#
#*****************************************************************************************
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "./tcl-import"
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
# Set the project name
set project_name "audioOutAXI"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
set project_name $::user_project_name
}
variable script_file
set script_file "build.tcl"
# Help information for this script
proc help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--project_name <name>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--project_name <name>\] Create project with the specified name. Default"
puts " name is the name of the project from where this"
puts " script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < [llength $::argc]} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--project_name" { incr i; set project_name [lindex $::argv $i] }
"--help" { help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/"]"
# Create project
create_project ${project_name} ./${project_name} -part xc7z020clg484-1
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Reconstruct message rules
# None
# Set project properties
set obj [current_project]
set_property -name "board_part" -value "em.avnet.com:zed:part0:0.9" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${project_name}.cache/ip" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "target_language" -value "VHDL" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
# Set IP repository paths
set obj [get_filesets sources_1]
set_property "ip_repo_paths" "[file normalize "$origin_dir/ZedBoardAudio-master"] [file normalize "$origin_dir/AXI_VGA_1.0"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
# Import local files from the original project
set files [list \
"[file normalize "$origin_dir/audioOutAXI.srcs/sources_1/imports/imports/myNote.vhd"]"\
"[file normalize "$origin_dir/audioOutAXI.srcs/sources_1/imports/counter.vhd"]"\
"[file normalize "$origin_dir/audioOutAXI.srcs/sources_1/imports/debouncer.vhd"]"\
"[file normalize "$origin_dir/audioOutAXI.srcs/sources_1/imports/dflipflop.vhd"]"\
"[file normalize "$origin_dir/audioOutAXI.srcs/sources_1/new/genericDebouncer.vhdl"]"\
"[file normalize "$origin_dir/audioOutAXI.srcs/sources_1/new/beatDetector.vhd"]"\
"[file normalize "$origin_dir/audioOutAXI.srcs/sources_1/new/audioMixing.vhd"]"\
"[file normalize "$origin_dir/audioOutAXI.srcs/sources_1/bd/audioTest/hdl/audioTest_wrapper.vhd"]"\
"[file normalize "$origin_dir/audioOutAXI.srcs/sources_1/new/debouncer5.vhd"]"\
]
set imported_files [import_files -fileset sources_1 $files]
# Set 'sources_1' fileset file properties for remote files
# None
# Set 'sources_1' fileset file properties for local files
set file "imports/myNote.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set file "imports/counter.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set file "imports/debouncer.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set file "imports/dflipflop.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set file "new/genericDebouncer.vhdl"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set file "new/beatDetector.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set file "new/audioMixing.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set file "hdl/audioTest_wrapper.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
set file "new/debouncer5.vhd"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "VHDL" -objects $file_obj
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "top" -value "audioTest_wrapper" -objects $obj
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
create_fileset -constrset constrs_1
}
# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]
# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/audioOutAXI.srcs/constrs_1/imports/ZedBoardAudio-master/constraintAudio.xdc"]"
set file_imported [import_files -fileset constrs_1 $file]
set file "ZedBoardAudio-master/constraintAudio.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
create_fileset -simset sim_1
}
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Empty (no sources present)
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "top" -value "audioTest_wrapper" -objects $obj
# Adding sources referenced in BDs, if not already added
if { [get_files myNote.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/imports/myNote.vhd
}
if { [get_files counter.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/counter.vhd
}
if { [get_files debouncer.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/debouncer.vhd
}
if { [get_files dflipflop.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/dflipflop.vhd
}
if { [get_files genericDebouncer.vhdl] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/genericDebouncer.vhdl
}
if { [get_files counter.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/counter.vhd
}
if { [get_files debouncer.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/debouncer.vhd
}
if { [get_files dflipflop.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/imports/dflipflop.vhd
}
if { [get_files genericDebouncer.vhdl] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/genericDebouncer.vhdl
}
if { [get_files beatDetector.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/beatDetector.vhd
}
if { [get_files beatDetector.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/beatDetector.vhd
}
if { [get_files audioMixing.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/audioMixing.vhd
}
if { [get_files beatDetector.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/beatDetector.vhd
}
if { [get_files beatDetector.vhd] == "" } {
import_files -quiet -fileset sources_1 D:/github/audioOutAXI/audioOutAXI.srcs/sources_1/new/beatDetector.vhd
}
# Proc to create BD audioTest
proc cr_bd_audioTest { parentCell } {
# The design that will be created by this Tcl proc contains the following
# module references:
# audioMixing, beatDetector, beatDetector, beatDetector, beatDetector, myNote, genericDebouncer, genericDebouncer
# CHANGE DESIGN NAME HERE
set design_name audioTest
common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
sfu.ca:user:AXI_VGA:1.0\
me:user:AudioInOut16:1.0\
xilinx.com:ip:axi_dma:7.1\
xilinx.com:ip:axi_gpio:2.0\
xilinx.com:ip:smartconnect:1.0\
xilinx.com:ip:cmpy:6.0\
xilinx.com:ip:xlconcat:2.1\
xilinx.com:ip:xlconstant:1.1\
xilinx.com:ip:processing_system7:5.5\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:xlslice:1.0\
xilinx.com:ip:xfft:9.0\
"
set list_ips_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
##################################################################
# CHECK Modules
##################################################################
set bCheckModules 1
if { $bCheckModules == 1 } {
set list_check_mods "\
audioMixing\
beatDetector\
beatDetector\
beatDetector\
beatDetector\
myNote\
genericDebouncer\
genericDebouncer\
"
set list_mods_missing ""
common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
lappend list_mods_missing $mod_vlnv
}
}
if { $list_mods_missing ne "" } {
catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_msg_id "BD_TCL-008" "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
variable script_folder
if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]
# Create ports
set AC_ADR0 [ create_bd_port -dir O AC_ADR0 ]
set AC_ADR1 [ create_bd_port -dir O AC_ADR1 ]
set AC_GPIO0 [ create_bd_port -dir O AC_GPIO0 ]
set AC_GPIO1 [ create_bd_port -dir I AC_GPIO1 ]
set AC_GPIO2 [ create_bd_port -dir I AC_GPIO2 ]
set AC_GPIO3 [ create_bd_port -dir I AC_GPIO3 ]
set AC_MCLK [ create_bd_port -dir O AC_MCLK ]
set AC_SCK [ create_bd_port -dir O AC_SCK ]
set AC_SDA [ create_bd_port -dir IO AC_SDA ]
set CLK_100 [ create_bd_port -dir I CLK_100 ]
set JC1_N [ create_bd_port -dir O JC1_N ]
set JC1_P [ create_bd_port -dir O JC1_P ]
set JC2_N [ create_bd_port -dir O JC2_N ]
set JC2_P [ create_bd_port -dir O JC2_P ]
set JC3_N [ create_bd_port -dir O JC3_N ]
set JC3_P [ create_bd_port -dir O JC3_P ]
set JC4_N [ create_bd_port -dir O JC4_N ]
set JC4_P [ create_bd_port -dir O JC4_P ]
set LD0 [ create_bd_port -dir O LD0 ]
set LD1 [ create_bd_port -dir O LD1 ]
set LD2 [ create_bd_port -dir O LD2 ]
set LD3 [ create_bd_port -dir O LD3 ]
set LD4 [ create_bd_port -dir O LD4 ]
set LD5 [ create_bd_port -dir O LD5 ]
set LD6 [ create_bd_port -dir O LD6 ]
set LD7 [ create_bd_port -dir O LD7 ]
set VGA_B [ create_bd_port -dir O -from 3 -to 0 VGA_B ]
set VGA_G [ create_bd_port -dir O -from 3 -to 0 VGA_G ]
set VGA_HSYNC [ create_bd_port -dir O VGA_HSYNC ]
set VGA_R [ create_bd_port -dir O -from 3 -to 0 VGA_R ]
set VGA_VSYNC [ create_bd_port -dir O VGA_VSYNC ]
set btns_5bits [ create_bd_port -dir I -from 4 -to 0 btns_5bits ]
set sws_8bits [ create_bd_port -dir I -from 7 -to 0 sws_8bits ]
# Create instance: AXI_VGA_0, and set properties
set AXI_VGA_0 [ create_bd_cell -type ip -vlnv sfu.ca:user:AXI_VGA:1.0 AXI_VGA_0 ]
# Create instance: AudioInOut16_0, and set properties
set AudioInOut16_0 [ create_bd_cell -type ip -vlnv me:user:AudioInOut16:1.0 AudioInOut16_0 ]
# Create instance: audioMixer, and set properties
set block_name audioMixing
set block_cell_name audioMixer
if { [catch {set audioMixer [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $audioMixer eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: axi_dma_fft, and set properties
set axi_dma_fft [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_fft ]
set_property -dict [ list \
CONFIG.c_include_sg {0} \
CONFIG.c_m_axi_mm2s_data_width {64} \
CONFIG.c_m_axis_mm2s_tdata_width {64} \
CONFIG.c_mm2s_burst_size {8} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {20} \
] $axi_dma_fft
# Create instance: axi_dma_mixer, and set properties
set axi_dma_mixer [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_mixer ]
set_property -dict [ list \
CONFIG.c_include_sg {0} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {20} \
] $axi_dma_mixer
# Create instance: axi_dma_mixer_recorded_sounds, and set properties
set axi_dma_mixer_recorded_sounds [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_mixer_recorded_sounds ]
set_property -dict [ list \
CONFIG.c_include_s2mm {0} \
CONFIG.c_include_sg {0} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {20} \
] $axi_dma_mixer_recorded_sounds
# Create instance: axi_dma_mixer_stored_sounds, and set properties
set axi_dma_mixer_stored_sounds [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_mixer_stored_sounds ]
set_property -dict [ list \
CONFIG.c_include_s2mm {0} \
CONFIG.c_include_sg {0} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {20} \
] $axi_dma_mixer_stored_sounds
# Create instance: axi_dma_vga, and set properties
set axi_dma_vga [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_dma_vga ]
set_property -dict [ list \
CONFIG.c_include_s2mm {0} \
CONFIG.c_include_sg {0} \
CONFIG.c_mm2s_burst_size {64} \
CONFIG.c_sg_include_stscntrl_strm {0} \
CONFIG.c_sg_length_width {20} \
] $axi_dma_vga
# Create instance: axi_gpio_beatDetector01_config, and set properties
set axi_gpio_beatDetector01_config [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_beatDetector01_config ]
set_property -dict [ list \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_ALL_OUTPUTS_2 {1} \
CONFIG.C_GPIO2_WIDTH {14} \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_beatDetector01_config
# Create instance: axi_gpio_beatDetector02_config, and set properties
set axi_gpio_beatDetector02_config [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_beatDetector02_config ]
set_property -dict [ list \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_ALL_OUTPUTS_2 {1} \
CONFIG.C_GPIO2_WIDTH {14} \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_beatDetector02_config
# Create instance: axi_gpio_beatDetector03_config, and set properties
set axi_gpio_beatDetector03_config [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_beatDetector03_config ]
set_property -dict [ list \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_ALL_OUTPUTS_2 {1} \
CONFIG.C_GPIO2_WIDTH {14} \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_beatDetector03_config
# Create instance: axi_gpio_beatDetector04_config, and set properties
set axi_gpio_beatDetector04_config [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_beatDetector04_config ]
set_property -dict [ list \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_ALL_OUTPUTS_2 {1} \
CONFIG.C_GPIO2_WIDTH {14} \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_beatDetector04_config
# Create instance: axi_gpio_buttons, and set properties
set axi_gpio_buttons [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_buttons ]
set_property -dict [ list \
CONFIG.C_ALL_INPUTS {1} \
CONFIG.C_GPIO_WIDTH {5} \
CONFIG.C_INTERRUPT_PRESENT {1} \
CONFIG.GPIO_BOARD_INTERFACE {Custom} \
CONFIG.USE_BOARD_FLOW {true} \
] $axi_gpio_buttons
# Create instance: axi_gpio_fft_config, and set properties
set axi_gpio_fft_config [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_fft_config ]
set_property -dict [ list \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_ALL_OUTPUTS_2 {1} \
CONFIG.C_GPIO2_WIDTH {1} \
CONFIG.C_GPIO_WIDTH {32} \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_fft_config
# Create instance: axi_gpio_middleC, and set properties
set axi_gpio_middleC [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_middleC ]
set_property -dict [ list \
CONFIG.C_ALL_OUTPUTS_2 {1} \
CONFIG.C_GPIO2_WIDTH {16} \
CONFIG.C_GPIO_WIDTH {16} \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_middleC
# Create instance: axi_gpio_play_interrupt, and set properties
set axi_gpio_play_interrupt [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_play_interrupt ]
set_property -dict [ list \
CONFIG.C_ALL_OUTPUTS {1} \
CONFIG.C_ALL_OUTPUTS_2 {1} \
CONFIG.C_GPIO2_WIDTH {1} \
CONFIG.C_GPIO_WIDTH {1} \
CONFIG.C_IS_DUAL {1} \
] $axi_gpio_play_interrupt
# Create instance: axi_gpio_switches, and set properties
set axi_gpio_switches [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_switches ]
set_property -dict [ list \
CONFIG.C_ALL_INPUTS {1} \
CONFIG.C_GPIO_WIDTH {8} \
CONFIG.C_INTERRUPT_PRESENT {1} \
CONFIG.GPIO_BOARD_INTERFACE {Custom} \
CONFIG.USE_BOARD_FLOW {true} \
] $axi_gpio_switches
# Create instance: axi_smc, and set properties
set axi_smc [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 axi_smc ]
set_property -dict [ list \
CONFIG.NUM_SI {7} \
] $axi_smc
# Create instance: beatDetector01, and set properties
set block_name beatDetector
set block_cell_name beatDetector01
if { [catch {set beatDetector01 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $beatDetector01 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
set_property -dict [ list \
CONFIG.bin {3} \
CONFIG.threshold {524288} \
] $beatDetector01
# Create instance: beatDetector02, and set properties
set block_name beatDetector
set block_cell_name beatDetector02
if { [catch {set beatDetector02 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $beatDetector02 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
set_property -dict [ list \
CONFIG.bin {3} \
CONFIG.threshold {524288} \
] $beatDetector02
# Create instance: beatDetector03, and set properties
set block_name beatDetector
set block_cell_name beatDetector03
if { [catch {set beatDetector03 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $beatDetector03 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: beatDetector04, and set properties
set block_name beatDetector
set block_cell_name beatDetector04
if { [catch {set beatDetector04 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $beatDetector04 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: complexMultipler04, and set properties
set complexMultipler04 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmpy:6.0 complexMultipler04 ]
set_property -dict [ list \
CONFIG.FlowControl {Blocking} \
CONFIG.MinimumLatency {7} \
CONFIG.OptimizeGoal {Performance} \
CONFIG.OutputWidth {32} \
] $complexMultipler04
# Create instance: complexMultiplier01, and set properties
set complexMultiplier01 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmpy:6.0 complexMultiplier01 ]
set_property -dict [ list \
CONFIG.FlowControl {Blocking} \
CONFIG.MinimumLatency {7} \
CONFIG.OptimizeGoal {Performance} \
CONFIG.OutputWidth {32} \
] $complexMultiplier01
# Create instance: complexMultiplier02, and set properties
set complexMultiplier02 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmpy:6.0 complexMultiplier02 ]
set_property -dict [ list \
CONFIG.FlowControl {Blocking} \
CONFIG.MinimumLatency {7} \
CONFIG.OptimizeGoal {Performance} \
CONFIG.OutputWidth {32} \
] $complexMultiplier02
# Create instance: complexMultiplier03, and set properties
set complexMultiplier03 [ create_bd_cell -type ip -vlnv xilinx.com:ip:cmpy:6.0 complexMultiplier03 ]
set_property -dict [ list \
CONFIG.FlowControl {Blocking} \
CONFIG.MinimumLatency {7} \
CONFIG.OptimizeGoal {Performance} \
CONFIG.OutputWidth {32} \
] $complexMultiplier03
# Create instance: concatBeatDetector01Config, and set properties
set concatBeatDetector01Config [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concatBeatDetector01Config ]
# Create instance: concatBeatDetector02Config, and set properties
set concatBeatDetector02Config [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concatBeatDetector02Config ]
# Create instance: concatBeatDetector03Config, and set properties
set concatBeatDetector03Config [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concatBeatDetector03Config ]
# Create instance: concatBeatDetector04Config, and set properties
set concatBeatDetector04Config [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concatBeatDetector04Config ]
# Create instance: concat_interrupts, and set properties
set concat_interrupts [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 concat_interrupts ]
set_property -dict [ list \
CONFIG.NUM_PORTS {3} \
] $concat_interrupts
# Create instance: constant_amplHigh, and set properties
set constant_amplHigh [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_amplHigh ]
set_property -dict [ list \
CONFIG.CONST_VAL {0010000000000000} \
CONFIG.CONST_WIDTH {16} \
] $constant_amplHigh
# Create instance: constant_amplLow, and set properties
set constant_amplLow [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_amplLow ]
set_property -dict [ list \
CONFIG.CONST_VAL {1010000000000000} \
CONFIG.CONST_WIDTH {16} \
] $constant_amplLow
# Create instance: constant_noReset, and set properties
set constant_noReset [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 constant_noReset ]
set_property -dict [ list \
CONFIG.CONST_VAL {0} \
] $constant_noReset
# Create instance: myNoteMiddleC, and set properties
set block_name myNote
set block_cell_name myNoteMiddleC
if { [catch {set myNoteMiddleC [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $myNoteMiddleC eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
set_property -dict [ list \
CONFIG.busWidth {16} \
CONFIG.frequency {262} \
] $myNoteMiddleC
# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list \
CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {400.000000} \
CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \
CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \
CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \
CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \
CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \
CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {66.666672} \
CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {66.666672} \
CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {66.666672} \
CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {66.666672} \
CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {66.666672} \
CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {66.666672} \
CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {50.000000} \
CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \
CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {66.666672} \
CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \
CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {400} \
CONFIG.PCW_ARMPLL_CTRL_FBDIV {48} \
CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \
CONFIG.PCW_CAN0_GRP_CLK_ENABLE {0} \
CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \
CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \
CONFIG.PCW_CAN0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \
CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \
CONFIG.PCW_CAN1_GRP_CLK_ENABLE {0} \
CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \
CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \
CONFIG.PCW_CAN1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \
CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \
CONFIG.PCW_CLK0_FREQ {100000000} \
CONFIG.PCW_CLK1_FREQ {10000000} \
CONFIG.PCW_CLK2_FREQ {10000000} \
CONFIG.PCW_CLK3_FREQ {10000000} \
CONFIG.PCW_CORE0_FIQ_INTR {0} \
CONFIG.PCW_CORE0_IRQ_INTR {0} \
CONFIG.PCW_CORE1_FIQ_INTR {0} \
CONFIG.PCW_CORE1_IRQ_INTR {0} \
CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \
CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1600.000} \
CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \
CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {4} \
CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {33.333333} \
CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \
CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \
CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \
CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \
CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \
CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \
CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \
CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \
CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \
CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \
CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \
CONFIG.PCW_DM_WIDTH {4} \
CONFIG.PCW_DQS_WIDTH {4} \
CONFIG.PCW_DQ_WIDTH {32} \
CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \
CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \
CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \
CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \
CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \
CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \
CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \
CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \
CONFIG.PCW_ENET0_RESET_ENABLE {0} \
CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \
CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \
CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \
CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \
CONFIG.PCW_ENET1_RESET_ENABLE {0} \
CONFIG.PCW_ENET_RESET_ENABLE {1} \
CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \
CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \
CONFIG.PCW_EN_4K_TIMER {0} \
CONFIG.PCW_EN_CAN0 {0} \
CONFIG.PCW_EN_CAN1 {0} \
CONFIG.PCW_EN_CLK0_PORT {1} \
CONFIG.PCW_EN_CLK1_PORT {0} \
CONFIG.PCW_EN_CLK2_PORT {0} \
CONFIG.PCW_EN_CLK3_PORT {0} \
CONFIG.PCW_EN_CLKTRIG0_PORT {0} \
CONFIG.PCW_EN_CLKTRIG1_PORT {0} \
CONFIG.PCW_EN_CLKTRIG2_PORT {0} \
CONFIG.PCW_EN_CLKTRIG3_PORT {0} \
CONFIG.PCW_EN_DDR {1} \
CONFIG.PCW_EN_EMIO_CAN0 {0} \
CONFIG.PCW_EN_EMIO_CAN1 {0} \
CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \
CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \
CONFIG.PCW_EN_EMIO_ENET0 {0} \
CONFIG.PCW_EN_EMIO_ENET1 {0} \
CONFIG.PCW_EN_EMIO_GPIO {0} \
CONFIG.PCW_EN_EMIO_I2C0 {0} \
CONFIG.PCW_EN_EMIO_I2C1 {0} \
CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \
CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \
CONFIG.PCW_EN_EMIO_PJTAG {0} \
CONFIG.PCW_EN_EMIO_SDIO0 {0} \
CONFIG.PCW_EN_EMIO_SDIO1 {0} \
CONFIG.PCW_EN_EMIO_SPI0 {0} \
CONFIG.PCW_EN_EMIO_SPI1 {0} \
CONFIG.PCW_EN_EMIO_SRAM_INT {0} \
CONFIG.PCW_EN_EMIO_TRACE {0} \
CONFIG.PCW_EN_EMIO_TTC0 {1} \
CONFIG.PCW_EN_EMIO_TTC1 {0} \
CONFIG.PCW_EN_EMIO_UART0 {0} \
CONFIG.PCW_EN_EMIO_UART1 {0} \
CONFIG.PCW_EN_EMIO_WDT {0} \
CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \
CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \
CONFIG.PCW_EN_ENET0 {1} \
CONFIG.PCW_EN_ENET1 {0} \
CONFIG.PCW_EN_GPIO {1} \
CONFIG.PCW_EN_I2C0 {0} \
CONFIG.PCW_EN_I2C1 {0} \
CONFIG.PCW_EN_MODEM_UART0 {0} \
CONFIG.PCW_EN_MODEM_UART1 {0} \
CONFIG.PCW_EN_PJTAG {0} \
CONFIG.PCW_EN_PTP_ENET0 {0} \
CONFIG.PCW_EN_PTP_ENET1 {0} \
CONFIG.PCW_EN_QSPI {1} \
CONFIG.PCW_EN_RST0_PORT {1} \
CONFIG.PCW_EN_RST1_PORT {0} \
CONFIG.PCW_EN_RST2_PORT {0} \
CONFIG.PCW_EN_RST3_PORT {0} \
CONFIG.PCW_EN_SDIO0 {1} \
CONFIG.PCW_EN_SDIO1 {0} \
CONFIG.PCW_EN_SMC {0} \
CONFIG.PCW_EN_SPI0 {0} \
CONFIG.PCW_EN_SPI1 {0} \
CONFIG.PCW_EN_TRACE {0} \
CONFIG.PCW_EN_TTC0 {1} \
CONFIG.PCW_EN_TTC1 {0} \
CONFIG.PCW_EN_UART0 {0} \
CONFIG.PCW_EN_UART1 {1} \
CONFIG.PCW_EN_USB0 {1} \
CONFIG.PCW_EN_USB1 {0} \
CONFIG.PCW_EN_WDT {0} \
CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \
CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \
CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \
CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \
CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \
CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \
CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \
CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {150.000000} \
CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \
CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
CONFIG.PCW_GP0_EN_MODIFIABLE_TXN {1} \
CONFIG.PCW_GP0_NUM_READ_THREADS {4} \
CONFIG.PCW_GP0_NUM_WRITE_THREADS {4} \
CONFIG.PCW_GP1_EN_MODIFIABLE_TXN {1} \
CONFIG.PCW_GP1_NUM_READ_THREADS {4} \
CONFIG.PCW_GP1_NUM_WRITE_THREADS {4} \
CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \
CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \
CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \
CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \
CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \
CONFIG.PCW_I2C0_GRP_INT_ENABLE {0} \
CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \
CONFIG.PCW_I2C0_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_I2C0_RESET_ENABLE {0} \
CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \
CONFIG.PCW_I2C1_GRP_INT_ENABLE {0} \
CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \
CONFIG.PCW_I2C1_PERIPHERAL_ENABLE {0} \
CONFIG.PCW_I2C1_RESET_ENABLE {0} \
CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
CONFIG.PCW_I2C_RESET_ENABLE {1} \
CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \
CONFIG.PCW_IMPORT_BOARD_PRESET {None} \
CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \
CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \
CONFIG.PCW_IOPLL_CTRL_FBDIV {30} \
CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \
CONFIG.PCW_IRQ_F2P_INTR {1} \
CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \
CONFIG.PCW_MIO_0_DIRECTION {inout} \
CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_0_PULLUP {disabled} \
CONFIG.PCW_MIO_0_SLEW {slow} \
CONFIG.PCW_MIO_10_DIRECTION {inout} \
CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_10_PULLUP {disabled} \
CONFIG.PCW_MIO_10_SLEW {slow} \
CONFIG.PCW_MIO_11_DIRECTION {inout} \
CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_11_PULLUP {disabled} \
CONFIG.PCW_MIO_11_SLEW {slow} \
CONFIG.PCW_MIO_12_DIRECTION {inout} \
CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_12_PULLUP {disabled} \
CONFIG.PCW_MIO_12_SLEW {slow} \
CONFIG.PCW_MIO_13_DIRECTION {inout} \
CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_13_PULLUP {disabled} \
CONFIG.PCW_MIO_13_SLEW {slow} \
CONFIG.PCW_MIO_14_DIRECTION {inout} \
CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_14_PULLUP {disabled} \
CONFIG.PCW_MIO_14_SLEW {slow} \
CONFIG.PCW_MIO_15_DIRECTION {inout} \
CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \
CONFIG.PCW_MIO_15_PULLUP {disabled} \
CONFIG.PCW_MIO_15_SLEW {slow} \
CONFIG.PCW_MIO_16_DIRECTION {out} \
CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_16_PULLUP {disabled} \
CONFIG.PCW_MIO_16_SLEW {fast} \
CONFIG.PCW_MIO_17_DIRECTION {out} \
CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \
CONFIG.PCW_MIO_17_PULLUP {disabled} \
CONFIG.PCW_MIO_17_SLEW {fast} \
CONFIG.PCW_MIO_18_DIRECTION {out} \
CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \