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Request help with updating Xilinx Zynq drivers #1225

Answered by mike919192
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I finally found that the issue was in the SetUpSLCRDivisors function. The macro XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 and similar no longer exist, so the variable SlcrDiv0 was never getting initialized and garbage was being written to register SLCR_GEM0_CLK_CTRL_ADDR.

I checked the example xilinx code and the register is never written to with the new drivers so something like this can be done.

/* SDT drivers should not write to the register */
#ifndef SDT
    SlcrTxClkCntrl = *( volatile unsigned int * ) ( slcrBaseAddress );
    SlcrTxClkCntrl &= EMACPS_SLCR_DIV_MASK;
    SlcrTxClkCntrl |= ( SlcrDiv1 << 20 );
    SlcrTxClkCntrl |= ( SlcrDiv0 << 8 );
    *( volatile unsigned int * ) …

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