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[clang-format] Recognize Verilog edge identifiers
Previously the event expression would be misidentified as a port list. A line break would be added after the comma. The events can be separated with either a comma or the `or` keyword, and a line break would not be inserted if the `or` keyword was used. We changed the behavior of the comma to match the `or` keyword. Before: ``` always @(posedge x, posedge y) x <= x; always @(posedge x or posedge y) x <= x; ``` After: ``` always @(posedge x, posedge y) x <= x; always @(posedge x or posedge y) x <= x; ``` Reviewed By: HazardyKnusperkeks Differential Revision: https://reviews.llvm.org/D149561
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3 files changed

+88
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‎clang/lib/Format/FormatToken.h

Lines changed: 71 additions & 126 deletions
Original file line numberDiff line numberDiff line change
@@ -1068,6 +1068,7 @@ struct AdditionalKeywords {
10681068
kw_delay_mode_zero = &IdentTable.get("delay_mode_zero");
10691069
kw_disable = &IdentTable.get("disable");
10701070
kw_dist = &IdentTable.get("dist");
1071+
kw_edge = &IdentTable.get("edge");
10711072
kw_elsif = &IdentTable.get("elsif");
10721073
kw_end = &IdentTable.get("end");
10731074
kw_end_keywords = &IdentTable.get("end_keywords");
@@ -1113,10 +1114,12 @@ struct AdditionalKeywords {
11131114
kw_macromodule = &IdentTable.get("macromodule");
11141115
kw_matches = &IdentTable.get("matches");
11151116
kw_medium = &IdentTable.get("medium");
1117+
kw_negedge = &IdentTable.get("negedge");
11161118
kw_nounconnected_drive = &IdentTable.get("nounconnected_drive");
11171119
kw_output = &IdentTable.get("output");
11181120
kw_packed = &IdentTable.get("packed");
11191121
kw_parameter = &IdentTable.get("parameter");
1122+
kw_posedge = &IdentTable.get("posedge");
11201123
kw_primitive = &IdentTable.get("primitive");
11211124
kw_priority = &IdentTable.get("priority");
11221125
kw_program = &IdentTable.get("program");
@@ -1198,132 +1201,71 @@ struct AdditionalKeywords {
11981201
// Some keywords are not included here because they don't need special
11991202
// treatment like `showcancelled` or they should be treated as identifiers
12001203
// like `int` and `logic`.
1201-
VerilogExtraKeywords =
1202-
std::unordered_set<IdentifierInfo *>({kw_always,
1203-
kw_always_comb,
1204-
kw_always_ff,
1205-
kw_always_latch,
1206-
kw_assert,
1207-
kw_assign,
1208-
kw_assume,
1209-
kw_automatic,
1210-
kw_before,
1211-
kw_begin,
1212-
kw_bins,
1213-
kw_binsof,
1214-
kw_casex,
1215-
kw_casez,
1216-
kw_celldefine,
1217-
kw_checker,
1218-
kw_clocking,
1219-
kw_constraint,
1220-
kw_cover,
1221-
kw_covergroup,
1222-
kw_coverpoint,
1223-
kw_disable,
1224-
kw_dist,
1225-
kw_end,
1226-
kw_endcase,
1227-
kw_endchecker,
1228-
kw_endclass,
1229-
kw_endclocking,
1230-
kw_endfunction,
1231-
kw_endgenerate,
1232-
kw_endgroup,
1233-
kw_endinterface,
1234-
kw_endmodule,
1235-
kw_endpackage,
1236-
kw_endprimitive,
1237-
kw_endprogram,
1238-
kw_endproperty,
1239-
kw_endsequence,
1240-
kw_endspecify,
1241-
kw_endtable,
1242-
kw_endtask,
1243-
kw_extends,
1244-
kw_final,
1245-
kw_foreach,
1246-
kw_forever,
1247-
kw_fork,
1248-
kw_function,
1249-
kw_generate,
1250-
kw_highz0,
1251-
kw_highz1,
1252-
kw_iff,
1253-
kw_ifnone,
1254-
kw_ignore_bins,
1255-
kw_illegal_bins,
1256-
kw_implements,
1257-
kw_import,
1258-
kw_initial,
1259-
kw_inout,
1260-
kw_input,
1261-
kw_inside,
1262-
kw_interconnect,
1263-
kw_interface,
1264-
kw_intersect,
1265-
kw_join,
1266-
kw_join_any,
1267-
kw_join_none,
1268-
kw_large,
1269-
kw_let,
1270-
kw_local,
1271-
kw_localparam,
1272-
kw_macromodule,
1273-
kw_matches,
1274-
kw_medium,
1275-
kw_output,
1276-
kw_package,
1277-
kw_packed,
1278-
kw_parameter,
1279-
kw_primitive,
1280-
kw_priority,
1281-
kw_program,
1282-
kw_property,
1283-
kw_pull0,
1284-
kw_pull1,
1285-
kw_pure,
1286-
kw_rand,
1287-
kw_randc,
1288-
kw_randcase,
1289-
kw_randsequence,
1290-
kw_ref,
1291-
kw_repeat,
1292-
kw_sample,
1293-
kw_scalared,
1294-
kw_sequence,
1295-
kw_small,
1296-
kw_soft,
1297-
kw_solve,
1298-
kw_specify,
1299-
kw_specparam,
1300-
kw_strong0,
1301-
kw_strong1,
1302-
kw_supply0,
1303-
kw_supply1,
1304-
kw_table,
1305-
kw_tagged,
1306-
kw_task,
1307-
kw_tri,
1308-
kw_tri0,
1309-
kw_tri1,
1310-
kw_triand,
1311-
kw_trior,
1312-
kw_trireg,
1313-
kw_unique,
1314-
kw_unique0,
1315-
kw_uwire,
1316-
kw_var,
1317-
kw_vectored,
1318-
kw_wand,
1319-
kw_weak0,
1320-
kw_weak1,
1321-
kw_wildcard,
1322-
kw_wire,
1323-
kw_with,
1324-
kw_wor,
1325-
kw_verilogHash,
1326-
kw_verilogHashHash});
1204+
VerilogExtraKeywords = std::unordered_set<IdentifierInfo *>(
1205+
{kw_always, kw_always_comb,
1206+
kw_always_ff, kw_always_latch,
1207+
kw_assert, kw_assign,
1208+
kw_assume, kw_automatic,
1209+
kw_before, kw_begin,
1210+
kw_bins, kw_binsof,
1211+
kw_casex, kw_casez,
1212+
kw_celldefine, kw_checker,
1213+
kw_clocking, kw_constraint,
1214+
kw_cover, kw_covergroup,
1215+
kw_coverpoint, kw_disable,
1216+
kw_dist, kw_edge,
1217+
kw_end, kw_endcase,
1218+
kw_endchecker, kw_endclass,
1219+
kw_endclocking, kw_endfunction,
1220+
kw_endgenerate, kw_endgroup,
1221+
kw_endinterface, kw_endmodule,
1222+
kw_endpackage, kw_endprimitive,
1223+
kw_endprogram, kw_endproperty,
1224+
kw_endsequence, kw_endspecify,
1225+
kw_endtable, kw_endtask,
1226+
kw_extends, kw_final,
1227+
kw_foreach, kw_forever,
1228+
kw_fork, kw_function,
1229+
kw_generate, kw_highz0,
1230+
kw_highz1, kw_iff,
1231+
kw_ifnone, kw_ignore_bins,
1232+
kw_illegal_bins, kw_implements,
1233+
kw_import, kw_initial,
1234+
kw_inout, kw_input,
1235+
kw_inside, kw_interconnect,
1236+
kw_interface, kw_intersect,
1237+
kw_join, kw_join_any,
1238+
kw_join_none, kw_large,
1239+
kw_let, kw_local,
1240+
kw_localparam, kw_macromodule,
1241+
kw_matches, kw_medium,
1242+
kw_negedge, kw_output,
1243+
kw_package, kw_packed,
1244+
kw_parameter, kw_posedge,
1245+
kw_primitive, kw_priority,
1246+
kw_program, kw_property,
1247+
kw_pull0, kw_pull1,
1248+
kw_pure, kw_rand,
1249+
kw_randc, kw_randcase,
1250+
kw_randsequence, kw_ref,
1251+
kw_repeat, kw_sample,
1252+
kw_scalared, kw_sequence,
1253+
kw_small, kw_soft,
1254+
kw_solve, kw_specify,
1255+
kw_specparam, kw_strong0,
1256+
kw_strong1, kw_supply0,
1257+
kw_supply1, kw_table,
1258+
kw_tagged, kw_task,
1259+
kw_tri, kw_tri0,
1260+
kw_tri1, kw_triand,
1261+
kw_trior, kw_trireg,
1262+
kw_unique, kw_unique0,
1263+
kw_uwire, kw_var,
1264+
kw_vectored, kw_wand,
1265+
kw_weak0, kw_weak1,
1266+
kw_wildcard, kw_wire,
1267+
kw_with, kw_wor,
1268+
kw_verilogHash, kw_verilogHashHash});
13271269
}
13281270

13291271
// Context sensitive keywords.
@@ -1462,6 +1404,7 @@ struct AdditionalKeywords {
14621404
IdentifierInfo *kw_disable;
14631405
IdentifierInfo *kw_dist;
14641406
IdentifierInfo *kw_elsif;
1407+
IdentifierInfo *kw_edge;
14651408
IdentifierInfo *kw_end;
14661409
IdentifierInfo *kw_end_keywords;
14671410
IdentifierInfo *kw_endcase;
@@ -1506,10 +1449,12 @@ struct AdditionalKeywords {
15061449
IdentifierInfo *kw_macromodule;
15071450
IdentifierInfo *kw_matches;
15081451
IdentifierInfo *kw_medium;
1452+
IdentifierInfo *kw_negedge;
15091453
IdentifierInfo *kw_nounconnected_drive;
15101454
IdentifierInfo *kw_output;
15111455
IdentifierInfo *kw_packed;
15121456
IdentifierInfo *kw_parameter;
1457+
IdentifierInfo *kw_posedge;
15131458
IdentifierInfo *kw_primitive;
15141459
IdentifierInfo *kw_priority;
15151460
IdentifierInfo *kw_program;

‎clang/unittests/Format/FormatTestVerilog.cpp

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1157,6 +1157,14 @@ TEST_F(FormatTestVerilog, StructuredProcedure) {
11571157
" x <= x;");
11581158
verifyFormat("always @(posedge x)\n"
11591159
" x <= x;");
1160+
verifyFormat("always @(posedge x or posedge y)\n"
1161+
" x <= x;");
1162+
verifyFormat("always @(posedge x, posedge y)\n"
1163+
" x <= x;");
1164+
verifyFormat("always @(negedge x, negedge y)\n"
1165+
" x <= x;");
1166+
verifyFormat("always @(edge x, edge y)\n"
1167+
" x <= x;");
11601168
verifyFormat("always\n"
11611169
" x <= x;");
11621170
verifyFormat("always @*\n"

‎clang/unittests/Format/TokenAnnotatorTest.cpp

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1684,6 +1684,15 @@ TEST_F(TokenAnnotatorTest, UnderstandsVerilogOperators) {
16841684
Tokens = Annotate("case (x) endcase;");
16851685
ASSERT_EQ(Tokens.size(), 7u) << Tokens;
16861686
EXPECT_TOKEN(Tokens[1], tok::l_paren, TT_ConditionLParen);
1687+
1688+
// Sensitivity list. The TT_Unknown type is clearly not binding for the
1689+
// future, please adapt if those tokens get annotated. This test is only here
1690+
// to prevent the comma from being annotated as TT_VerilogInstancePortComma.
1691+
Tokens = Annotate("always @(posedge x, posedge y);");
1692+
ASSERT_EQ(Tokens.size(), 11u) << Tokens;
1693+
EXPECT_TOKEN(Tokens[2], tok::l_paren, TT_Unknown);
1694+
EXPECT_TOKEN(Tokens[5], tok::comma, TT_Unknown);
1695+
EXPECT_TOKEN(Tokens[8], tok::r_paren, TT_Unknown);
16871696
}
16881697

16891698
TEST_F(TokenAnnotatorTest, UnderstandConstructors) {

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