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[RISCV] Make zve32f imply F and zve64d imply D.
The 1.0 vector spec PDF has text that says that Zve32f is compatible with F or Zfinx and that Zve64d is compatible with D and Zdinx. The references to *inx were removed from the spec in the github repository in October 2021. The 1.0 pdf was made in September 2021. Relevant commit riscvarchive/riscv-v-spec@6fedb86 Reviewed By: jacquesguan Differential Revision: https://reviews.llvm.org/D150021
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‎clang/test/Driver/riscv-arch.c

+1-23
Original file line numberDiff line numberDiff line change
@@ -218,16 +218,6 @@
218218
// RV32-ORDER: error: invalid arch name 'rv32imcq',
219219
// RV32-ORDER: standard user-level extension not given in canonical order 'q'
220220

221-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s \
222-
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE32F-ER %s
223-
// RV32-ZVE32F-ER: error: invalid arch name 'rv32izve32f',
224-
// RV32-ZVE32F-ER: 'zve32f' requires 'f' or 'zfinx' extension to also be specified
225-
226-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64d -### %s \
227-
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVE64D-ER %s
228-
// RV32-ZVE64D-ER: error: invalid arch name 'rv32ifzve64d',
229-
// RV32-ZVE64D-ER: 'zve64d' requires 'd' or 'zdinx' extension to also be specified
230-
231221
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izvl64b -### %s \
232222
// RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ZVL64B-ER %s
233223
// RV32-ZVL64B-ER: error: invalid arch name 'rv32izvl64b',
@@ -498,10 +488,6 @@
498488
// RV32-ZVE32X-GOODVERS: "-target-feature" "+zve32x"
499489

500490
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve32f -### %s -c 2>&1 | \
501-
// RUN: FileCheck -check-prefix=RV32-ZVE32F-REQUIRE-F %s
502-
// RV32-ZVE32F-REQUIRE-F: error: invalid arch name 'rv32izve32f', 'zve32f' requires 'f' or 'zfinx' extension to also be specified
503-
504-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve32f -### %s -c 2>&1 | \
505491
// RUN: FileCheck -check-prefix=RV32-ZVE32F-GOOD %s
506492
// RV32-ZVE32F-GOOD: "-target-feature" "+zve32f"
507493

@@ -510,18 +496,10 @@
510496
// RV32-ZVE64X: "-target-feature" "+zve64x"
511497

512498
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64f -### %s -c 2>&1 | \
513-
// RUN: FileCheck -check-prefix=RV32-ZVE64F-REQUIRE-F %s
514-
// RV32-ZVE64F-REQUIRE-F: error: invalid arch name 'rv32izve64f', 'zve32f' requires 'f' or 'zfinx' extension to also be specified
515-
516-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64f -### %s -c 2>&1 | \
517499
// RUN: FileCheck -check-prefix=RV32-ZVE64F-GOOD %s
518500
// RV32-ZVE64F-GOOD: "-target-feature" "+zve64f"
519501

520-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifzve64d -### %s -c 2>&1 | \
521-
// RUN: FileCheck -check-prefix=RV32-ZVE64D-REQUIRE-D %s
522-
// RV32-ZVE64D-REQUIRE-D: error: invalid arch name 'rv32ifzve64d', 'zve64d' requires 'd' or 'zdinx' extension to also be specified
523-
524-
// RUN: %clang --target=riscv32-unknown-elf -march=rv32ifdzve64d -### %s -c 2>&1 | \
502+
// RUN: %clang --target=riscv32-unknown-elf -march=rv32izve64d -### %s -c 2>&1 | \
525503
// RUN: FileCheck -check-prefix=RV32-ZVE64D-GOOD %s
526504
// RV32-ZVE64D-GOOD: "-target-feature" "+zve64d"
527505

‎llvm/docs/ReleaseNotes.rst

+2
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,8 @@ Changes to the RISC-V Backend
176176
RISCVTargetParser.h interface. Similar for ``parseTuneCPUkind`` and
177177
``checkTuneCPUKind``.
178178
* Add sifive-x280 processor.
179+
* Zve32f is no longer allowed with Zfinx. Zve64d is no longer allowed with
180+
Zdinx.
179181

180182
Changes to the WebAssembly Backend
181183
----------------------------------

‎llvm/lib/Support/RISCVISAInfo.cpp

+4-19
Original file line numberDiff line numberDiff line change
@@ -856,10 +856,7 @@ Error RISCVISAInfo::checkDependency() {
856856
bool HasD = Exts.count("d") != 0;
857857
bool HasF = Exts.count("f") != 0;
858858
bool HasZfinx = Exts.count("zfinx") != 0;
859-
bool HasZdinx = Exts.count("zdinx") != 0;
860859
bool HasVector = Exts.count("zve32x") != 0;
861-
bool HasZve32f = Exts.count("zve32f") != 0;
862-
bool HasZve64d = Exts.count("zve64d") != 0;
863860
bool HasZvl = MinVLen != 0;
864861
bool HasZcmt = Exts.count("zcmt") != 0;
865862
bool HasZcd = Exts.count("zcd") != 0;
@@ -868,22 +865,10 @@ Error RISCVISAInfo::checkDependency() {
868865
return createStringError(errc::invalid_argument,
869866
"'f' and 'zfinx' extensions are incompatible");
870867

871-
if (HasZve32f && !HasF && !HasZfinx)
868+
if (Exts.count("zvfh") && !Exts.count("zfh") && !Exts.count("zfhmin"))
872869
return createStringError(
873870
errc::invalid_argument,
874-
"'zve32f' requires 'f' or 'zfinx' extension to also be specified");
875-
876-
if (HasZve64d && !HasD && !HasZdinx)
877-
return createStringError(
878-
errc::invalid_argument,
879-
"'zve64d' requires 'd' or 'zdinx' extension to also be specified");
880-
881-
if (Exts.count("zvfh") && !Exts.count("zfh") && !Exts.count("zfhmin") &&
882-
!Exts.count("zhinx") && !Exts.count("zhinxmin"))
883-
return createStringError(
884-
errc::invalid_argument,
885-
"'zvfh' requires 'zfh', 'zfhmin', 'zhinx' or 'zhinxmin' extension to "
886-
"also be specified");
871+
"'zvfh' requires 'zfh' or 'zfhmin extension to also be specified");
887872

888873
if (HasZvl && !HasVector)
889874
return createStringError(
@@ -949,9 +934,9 @@ static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
949934
static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx",
950935
"zkne", "zknd", "zknh"};
951936
static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
952-
static const char *ImpliedExtsZve32f[] = {"zve32x"};
937+
static const char *ImpliedExtsZve32f[] = {"zve32x", "f"};
953938
static const char *ImpliedExtsZve32x[] = {"zvl32b", "zicsr"};
954-
static const char *ImpliedExtsZve64d[] = {"zve64f"};
939+
static const char *ImpliedExtsZve64d[] = {"zve64f", "d"};
955940
static const char *ImpliedExtsZve64f[] = {"zve64x", "zve32f"};
956941
static const char *ImpliedExtsZve64x[] = {"zve32x", "zvl64b"};
957942
static const char *ImpliedExtsZvfh[] = {"zve32f"};

‎llvm/lib/Target/RISCV/RISCVFeatures.td

+3-4
Original file line numberDiff line numberDiff line change
@@ -397,7 +397,7 @@ def FeatureStdExtZve32f
397397
: SubtargetFeature<"zve32f", "HasStdExtZve32f", "true",
398398
"'Zve32f' (Vector Extensions for Embedded Processors "
399399
"with maximal 32 EEW and F extension)",
400-
[FeatureStdExtZve32x]>;
400+
[FeatureStdExtZve32x, FeatureStdExtF]>;
401401

402402
def FeatureStdExtZve64x
403403
: SubtargetFeature<"zve64x", "HasStdExtZve64x", "true",
@@ -415,13 +415,12 @@ def FeatureStdExtZve64d
415415
: SubtargetFeature<"zve64d", "HasStdExtZve64d", "true",
416416
"'Zve64d' (Vector Extensions for Embedded Processors "
417417
"with maximal 64 EEW, F and D extension)",
418-
[FeatureStdExtZve64f]>;
418+
[FeatureStdExtZve64f, FeatureStdExtD]>;
419419

420420
def FeatureStdExtV
421421
: SubtargetFeature<"v", "HasStdExtV", "true",
422422
"'V' (Vector Extension for Application Processors)",
423-
[FeatureStdExtZvl128b, FeatureStdExtZve64d,
424-
FeatureStdExtF, FeatureStdExtD]>;
423+
[FeatureStdExtZvl128b, FeatureStdExtZve64d]>;
425424

426425
def HasVInstructions : Predicate<"Subtarget->hasVInstructions()">,
427426
AssemblerPredicate<

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