tu: Fix CP_BLIT sync on A7XX

A7XX needs the CCU caches to be flushed before a CP_BLIT to flush
any GMEM contents that may have been written out prior to the blit.
Without this, corruption can be seen with GMEM passes using CP_BLIT
especially when forced using `TU_DEBUG=gmem,unaligned_store`.

Signed-off-by: Mark Collins <[email protected]>

Author: PixelyIon

src/freedreno/vulkan/tu_clear_blit.cc

@@ -3703,9 +3703,14 @@ store_cp_blit(struct tu_cmd_buffer *cmd,
                    SP_PS_2D_SRC_PITCH(CHIP, .pitch = cmd->state.tiling->tile0.width * cpp));
 
    /* sync GMEM writes with CACHE. */
-   tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
+   if (CHIP >= A7XX) {
+      tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_FLUSH_COLOR);
+      tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_FLUSH_DEPTH);
+   } else {
+      tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
+   }
 
-   /* Wait for CACHE_INVALIDATE to land */
+   /* Wait for cache event to land */
    tu_cs_emit_wfi(cs);
 
    r2d_run(cmd, cs);