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Merge pull request #792 from yunyaobaihong/master
Decoder Update : cjtag , onewire_link and sbus
2 parents 88058f9 + 3b027ab commit 0957a05

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libsigrokdecode4DSL/decoders/cjtag/pd.py

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Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
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## Copyright (C) 2012-2020 Uwe Hermann <[email protected]>
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## Copyright (C) 2019 Zhiyuan Wan <[email protected]>
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## Copyright (C) 2019 Kongou Hikari <[email protected]>
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## Copyright (C) 2024 DreamSourceLab <[email protected]>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
@@ -19,6 +20,11 @@
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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##
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## 2024/8/7 DreamSourceLab : Display data when zooming out
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## 2024/8/16 DreamSourceLab : Added a filter to remove non-binary data
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##
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import sigrokdecode as srd
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from common.srdhelper import SrdStrEnum
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@@ -257,6 +263,7 @@ def handle_rising_tckc_edge(self, tdi, tdo, tck, tms):
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t = self.state.value[-2:] + ' TDI'
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b = ''.join(map(str, self.bits_tdi[1:]))
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b = ''.join(filter(lambda x: x in '01', b))
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h = ' (0x%x' % int('0b0' + b, 2) + ')'
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s = t + ': ' + b + h + ', ' + str(len(self.bits_tdi[1:])) + ' bits'
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self.putx_bs([30, [s]])
@@ -266,6 +273,7 @@ def handle_rising_tckc_edge(self, tdi, tdo, tck, tms):
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t = self.state.value[-2:] + ' TDO'
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b = ''.join(map(str, self.bits_tdo[1:]))
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b = ''.join(filter(lambda x: x in '01', b))
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h = ' (0x%x' % int('0b0' + b, 2) + ')'
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s = t + ': ' + b + h + ', ' + str(len(self.bits_tdo[1:])) + ' bits'
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self.putx_bs([31, [s]])

libsigrokdecode4DSL/decoders/onewire_link/pd.py

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@@ -17,6 +17,10 @@
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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##
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## 2024/7/30 DreamSourceLab : Allow adjustment of data structure and pulse width timing for high and low levels
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##
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import sigrokdecode as srd
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class SamplerateError(Exception):
@@ -60,11 +64,14 @@ class SamplerateError(Exception):
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True: 24.0,
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},
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},
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#Frame
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'SLOT': {
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#Frame End
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'min': {
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False: 60.0,
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True: 6.0,
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},
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#Frame Mid
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'max': {
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False: 120.0,
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True: 16.0,
@@ -77,10 +84,12 @@ class SamplerateError(Exception):
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},
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},
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'LOWR': {
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# if time < min , is too short
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'min': {
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False: 1.0,
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True: 1.0,
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},
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# if time > max , bit = 1, else bit = 0
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'max': {
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False: 15.0,
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True: 2.0,
@@ -104,6 +113,12 @@ class Decoder(srd.Decoder):
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options = (
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{'id': 'overdrive', 'desc': 'Start in overdrive speed',
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'default': 'no', 'values': ('yes', 'no'), 'idn':'dec_onewire_link_opt_overdrive'},
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{'id': 'min height level pulse time', 'desc': 'min height level pulse time(us)',
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'default': 2.0, 'idn':'dec_onewire_link_opt_min_height_level_pulse_time'},
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{'id': 'min overdrive height level pulse time', 'desc': 'min overdrive height level pulse time(us)',
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'default': 15.0, 'idn':'dec_onewire_link_opt_min_overdrive_height_level_pulse_time'},
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{'id': 'data order', 'desc': 'data order',
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'default': 'bit first', 'values': ('bit first', 'space first'),'idn':'dec_can_opt_data_order'},
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)
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annotations = (
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('bit', 'Bit'),
@@ -129,13 +144,18 @@ def reset(self):
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self.bit_count = -1
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self.command = 0
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self.overdrive = False
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self.bit_first = True
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self.fall = 0
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self.rise = 0
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def start(self):
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self.out_python = self.register(srd.OUTPUT_PYTHON)
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self.out_ann = self.register(srd.OUTPUT_ANN)
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self.overdrive = (self.options['overdrive'] == 'yes')
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self.bit_first = (self.options['data order'] == 'bit first')
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timing['LOWR']['max'][False] = float(self.options['min height level pulse time'])
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timing['LOWR']['max'][True] = float(self.options['min overdrive height level pulse time'])
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self.fall = 0
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self.rise = 0
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self.bit_count = -1
@@ -188,6 +208,19 @@ def wait_falling_timeout(self, start, t):
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samples_to_skip = samples_to_skip if (samples_to_skip > 0) else 0
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return self.wait([{0: 'f'}, {'skip': samples_to_skip}])
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def MinBitTimeOutput(self, time):
212+
if time < timing['LOWR']['min'][self.overdrive]:
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self.putfr([1, ['Low signal not long enough',
214+
'Low too short',
215+
'LOW < ' + str(timing['LOWR']['min'][self.overdrive])]])
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217+
def GetBitValue(self, time):
218+
if time > timing['LOWR']['max'][self.overdrive]:
219+
self.bit = 1 #Long pulse is a 1 bit.
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else:
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self.bit = 0 #Short pulse is a 0 bit.
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def decode(self):
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if not self.samplerate:
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raise SamplerateError('Cannot decode without samplerate.')
@@ -237,16 +270,13 @@ def decode(self):
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# Overdrive reset pulse.
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self.putfr([2, ['Reset', 'Rst', 'R']])
239272
self.state = 'PRESENCE DETECT HIGH'
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#Frame
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elif time < timing['SLOT']['max'][self.overdrive]:
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# Read/write time slot.
242-
if time < timing['LOWR']['min'][self.overdrive]:
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self.putfr([1, ['Low signal not long enough',
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'Low too short',
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'LOW < ' + str(timing['LOWR']['min'][self.overdrive])]])
246-
if time < timing['LOWR']['max'][self.overdrive]:
247-
self.bit = 1 # Short pulse is a 1 bit.
248-
else:
249-
self.bit = 0 # Long pulse is a 0 bit.
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if self.bit_first == True:
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# Read/write time slot.
277+
self.MinBitTimeOutput(time)
278+
self.GetBitValue(time)
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# Wait for end of slot.
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self.state = 'SLOT'
252282
else:
@@ -305,6 +335,12 @@ def decode(self):
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self.state = 'LOW'
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else: # End of time slot.
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# Output bit.
338+
if self.bit_first == False:
339+
time = ((self.samplenum - self.rise) / self.samplerate) * 1000000.0
340+
# Read/write time slot.
341+
self.MinBitTimeOutput(time)
342+
self.GetBitValue(time)
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308344
self.putfs([0, ['Bit: %d' % self.bit, '%d' % self.bit]])
309345
self.putpfs(['BIT', self.bit])
310346
# Save command bits.

libsigrokdecode4DSL/decoders/sbus_futaba/pd.py

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@@ -2,6 +2,7 @@
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## This file is part of the libsigrokdecode project.
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##
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## Copyright (C) 2022 Gerhard Sittig <[email protected]>
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## Copyright (C) 2024 DreamSourceLab <[email protected]>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## along with this program; if not, see <http://www.gnu.org/licenses/>.
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##
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##
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## 2024/7/5 DreamSourceLab : Fixing the issue of decoding only the first frame
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##
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"""
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OUTPUT_PYTHON format:
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@@ -223,6 +228,7 @@ def flush_accum_bits(self):
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# spans all unprocessed data, and improves perception.
224229
if self.sent_fields >= upto:
225230
self.msg_complete = True
231+
self.sent_fields = 0
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if self.msg_complete and self.bits_accum:
227233
self.failed = ['Excess data bits', 'Excess']
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