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‎2-1 STM32_Template/DebugConfig/Target_1_STM32F101C8_1.0.0.dbgconf

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// <<< Use Configuration Wizard in Context Menu >>>
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// <h> Debug MCU Configuration
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// <o0.0> DBG_SLEEP
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// <i> Debug Sleep Mode
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// <i> 0: (FCLK=On, HCLK=Off) FCLK is clocked by the system clock as previously configured by the software while HCLK is disabled
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// <i> 1: (FCLK=On, HCLK=On) HCLK is fed by the same clock that is provided to FCLK
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// <o0.1> DBG_STOP
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// <i> Debug Stop Mode
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// <i> 0: (FCLK=Off, HCLK=Off) Clock controller disables all clocks
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// <i> 1: (FCLK=On, HCLK=On) FCLK and HCLK are provided by the internal RC oscillator which remains active
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// <o0.2> DBG_STANDBY
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// <i> Debug Standby Mode
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// <i> 0: (FCLK=Off, HCLK=Off) The whole digital part is unpowered.
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// <i> 1: (FCLK=On, HCLK=On) Digital part is powered and FCLK and HCLK are provided by the internal RC oscillator which remains active
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// <o0.8> DBG_IWDG_STOP
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// <i> Debug independent watchdog stopped when core is halted
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// <i> 0: The watchdog counter clock continues even if the core is halted
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// <i> 1: The watchdog counter clock is stopped when the core is halted
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// <o0.9> DBG_WWDG_STOP
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// <i> Debug window watchdog stopped when core is halted
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// <i> 0: The window watchdog counter clock continues even if the core is halted
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// <i> 1: The window watchdog counter clock is stopped when the core is halted
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// <o0.10> DBG_TIM1_STOP
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// <i> Timer 1 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.11> DBG_TIM2_STOP
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// <i> Timer 2 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.12> DBG_TIM3_STOP
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// <i> Timer 3 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.13> DBG_TIM4_STOP
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// <i> Timer 4 counter stopped when core is halted
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// <i> 0: The clock of the involved Timer Counter is fed even if the core is halted
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// <i> 1: The clock of the involved Timer counter is stopped when the core is halted
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// <o0.14> DBG_CAN1_STOP
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// <i> Debug CAN1 stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: CAN1 receive registers are frozen
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// <o0.15> DBG_I2C1_SMBUS_TIMEOUT
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// <i> I2C1 SMBUS timeout mode stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The SMBUS timeout is frozen
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// <o0.16> DBG_I2C2_SMBUS_TIMEOUT
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// <i> I2C2 SMBUS timeout mode stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: The SMBUS timeout is frozen
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// <o0.17> DBG_TIM8_STOP
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// <i> Timer 8 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.18> DBG_TIM5_STOP
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// <i> Timer 5 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.19> DBG_TIM6_STOP
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// <i> Timer 6 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.20> DBG_TIM7_STOP
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// <i> Timer 7 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.21> DBG_CAN2_STOP
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// <i> Debug CAN2 stopped when Core is halted
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// <i> 0: Same behavior as in normal mode
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// <i> 1: CAN2 receive registers are frozen
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// <o0.25> DBG_TIM12_STOP
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// <i> Timer 12 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.26> DBG_TIM13_STOP
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// <i> Timer 13 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.27> DBG_TIM14_STOP
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// <i> Timer 14 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.28> DBG_TIM9_STOP
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// <i> Timer 9 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.29> DBG_TIM10_STOP
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// <i> Timer 10 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// <o0.30> DBG_TIM11_STOP
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// <i> Timer 11 counter stopped when core is halted
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// <i> 0: The clock of the involved timer counter is fed even if the core is halted, and the outputs behave normally.
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// <i> 1: The clock of the involved timer counter is stopped when the core is halted, and the outputs are disabled (as if there were an emergency stop in response to a break event).
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// </h>
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DbgMCU_CR = 0x00000007;
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// <<< end of configuration section >>>

‎2-1 STM32_Template/Library/misc.c

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/**
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******************************************************************************
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* @file misc.c
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* @author MCD Application Team
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* @version V3.5.0
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* @date 11-March-2011
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* @brief This file provides all the miscellaneous firmware functions (add-on
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* to CMSIS functions).
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "misc.h"
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/** @addtogroup STM32F10x_StdPeriph_Driver
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* @{
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*/
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/** @defgroup MISC
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* @brief MISC driver modules
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* @{
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*/
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/** @defgroup MISC_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup MISC_Private_Defines
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* @{
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*/
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#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
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/**
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* @}
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*/
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/** @defgroup MISC_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup MISC_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup MISC_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup MISC_Private_Functions
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* @{
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*/
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/**
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* @brief Configures the priority grouping: pre-emption priority and subpriority.
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* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
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* This parameter can be one of the following values:
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* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
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* 4 bits for subpriority
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* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
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* 3 bits for subpriority
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* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
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* 2 bits for subpriority
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* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
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* 1 bits for subpriority
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* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
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* 0 bits for subpriority
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* @retval None
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*/
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void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
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{
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/* Check the parameters */
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assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
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/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
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SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
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}
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/**
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* @brief Initializes the NVIC peripheral according to the specified
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* parameters in the NVIC_InitStruct.
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* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
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* the configuration information for the specified NVIC peripheral.
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* @retval None
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*/
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void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
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{
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uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
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/* Check the parameters */
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assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
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assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
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assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
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if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
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{
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/* Compute the Corresponding IRQ Priority --------------------------------*/
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tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
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tmppre = (0x4 - tmppriority);
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tmpsub = tmpsub >> tmppriority;
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tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
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tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
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tmppriority = tmppriority << 0x04;
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NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
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/* Enable the Selected IRQ Channels --------------------------------------*/
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NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
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(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
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}
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else
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{
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/* Disable the Selected IRQ Channels -------------------------------------*/
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NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
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(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
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}
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}
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/**
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* @brief Sets the vector table location and Offset.
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* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
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* This parameter can be one of the following values:
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* @arg NVIC_VectTab_RAM
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* @arg NVIC_VectTab_FLASH
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* @param Offset: Vector Table base offset field. This value must be a multiple
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* of 0x200.
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* @retval None
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*/
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void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
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{
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/* Check the parameters */
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assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
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assert_param(IS_NVIC_OFFSET(Offset));
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SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
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}
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/**
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* @brief Selects the condition for the system to enter low power mode.
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* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
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* This parameter can be one of the following values:
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* @arg NVIC_LP_SEVONPEND
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* @arg NVIC_LP_SLEEPDEEP
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* @arg NVIC_LP_SLEEPONEXIT
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* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_NVIC_LP(LowPowerMode));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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SCB->SCR |= LowPowerMode;
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}
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else
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{
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SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
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}
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}
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/**
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* @brief Configures the SysTick clock source.
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* @param SysTick_CLKSource: specifies the SysTick clock source.
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* This parameter can be one of the following values:
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* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
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* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
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* @retval None
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*/
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void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
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{
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/* Check the parameters */
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assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
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if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
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{
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SysTick->CTRL |= SysTick_CLKSource_HCLK;
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}
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else
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{
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SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
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}
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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