Merge branch 'main' of github.com:KhronosGroup/SPIRV-Headers into header_4_hlsl

Author: AnastaZIuk

include/spirv/spir-v.xml

@@ -90,7 +90,7 @@
         <id value="37"  vendor="heroseh" tool="Hero C Compiler" comment="https://github.com/heroseh/hcc"/>
         <id value="38"  vendor="Meta" tool="SparkSL" comment="Contact Dunfan Lu, [email protected], https://sparkar.facebook.com/ar-studio/learn/sparksl/sparksl-overview"/>
         <id value="39"  vendor="SirLynix" tool="Nazara ShaderLang Compiler" comment="Contact Jérôme Leclercq, https://github.com/NazaraEngine/ShaderLang"/>
-        <id value="40"  vendor="NVIDIA" tool="Slang Compiler" comment="Contact Theresa Foley, [email protected], https://github.com/shader-slang/slang/"/>
+        <id value="40"  vendor="Khronos" tool="Slang Compiler" comment="https://shader-slang.org"/>
         <id value="41"  vendor="Zig Software Foundation" tool="Zig Compiler" comment="Contact Robin Voetter, https://github.com/Snektron"/>
         <id value="42"  vendor="Rendong Liang" tool="spq" comment="Contact Rendong Liang, [email protected], https://github.com/PENGUINLIONG/spq-rs"/>
         <id value="43"  vendor="LLVM" tool="LLVM SPIR-V Backend" comment="Contact Michal Paszkowski, [email protected], https://github.com/llvm/llvm-project/tree/main/llvm/lib/Target/SPIRV"/>

include/spirv/unified1/NonSemanticClspvReflection.h

@@ -33,7 +33,7 @@ extern "C" {
 #endif
 
 enum {
-    NonSemanticClspvReflectionRevision = 6,
+    NonSemanticClspvReflectionRevision = 7,
     NonSemanticClspvReflectionRevision_BitWidthPadding = 0x7fffffff
 };
 
@@ -79,6 +79,7 @@ enum NonSemanticClspvReflectionInstructions {
     NonSemanticClspvReflectionPrintfBufferStorageBuffer = 39,
     NonSemanticClspvReflectionPrintfBufferPointerPushConstant = 40,
     NonSemanticClspvReflectionNormalizedSamplerMaskPushConstant = 41,
+    NonSemanticClspvReflectionWorkgroupVariableSize = 42,
     NonSemanticClspvReflectionInstructionsMax = 0x7fffffff
 };
 

include/spirv/unified1/extinst.nonsemantic.clspvreflection.grammar.json

@@ -1,5 +1,5 @@
 {
-  "revision" : 6,
+  "revision" : 7,
   "instructions" : [
     {
       "opname" : "Kernel",
@@ -405,6 +405,14 @@
       { "kind" : "IdRef", "name" : "Offset" },
       { "kind" : "IdRef", "name" : "Size" }
       ]
+    },
+    {
+    "opname" : "WorkgroupVariableSize",
+    "opcode" : 42,
+    "operands" : [
+      { "kind" : "IdRef", "name" : "Variable" },
+      { "kind" : "IdRef", "name" : "Size" }
+      ]
     }
   ],
   "operand_kinds" : [

include/spirv/unified1/spirv.bf

@@ -173,6 +173,8 @@ namespace Spv
             SignedZeroInfNanPreserve = 4461,
             RoundingModeRTE = 4462,
             RoundingModeRTZ = 4463,
+            NonCoherentTileAttachmentReadQCOM = 4489,
+            TileShadingRateQCOM = 4490,
             EarlyAndLateFragmentTestsAMD = 5017,
             StencilRefReplacingEXT = 5027,
             CoalescingAMDX = 5069,
@@ -243,6 +245,7 @@ namespace Spv
             Image = 11,
             StorageBuffer = 12,
             TileImageEXT = 4172,
+            TileAttachmentQCOM = 4491,
             NodePayloadAMDX = 5068,
             CallableDataKHR = 5328,
             CallableDataNV = 5328,
@@ -387,9 +390,15 @@ namespace Spv
             Float = 14,
             UnormInt24 = 15,
             UnormInt101010_2 = 16,
+            UnormInt10X6EXT = 17,
             UnsignedIntRaw10EXT = 19,
             UnsignedIntRaw12EXT = 20,
             UnormInt2_101010EXT = 21,
+            UnsignedInt10X6EXT = 22,
+            UnsignedInt12X4EXT = 23,
+            UnsignedInt14X2EXT = 24,
+            UnormInt12X4EXT = 25,
+            UnormInt14X2EXT = 26,
             Max = 0x7fffffff,
         }
 
@@ -731,6 +740,9 @@ namespace Spv
             DeviceIndex = 4438,
             ViewIndex = 4440,
             ShadingRateKHR = 4444,
+            TileOffsetQCOM = 4492,
+            TileDimensionQCOM = 4493,
+            TileApronSizeQCOM = 4494,
             BaryCoordNoPerspAMD = 4992,
             BaryCoordNoPerspCentroidAMD = 4993,
             BaryCoordNoPerspSampleAMD = 4994,
@@ -1133,6 +1145,7 @@ namespace Spv
             TextureSampleWeightedQCOM = 4484,
             TextureBoxFilterQCOM = 4485,
             TextureBlockMatchQCOM = 4486,
+            TileShadingQCOM = 4495,
             TextureBlockMatch2QCOM = 4498,
             Float16ImageAMD = 5008,
             ImageGatherBiasLodAMD = 5009,
@@ -1143,6 +1156,9 @@ namespace Spv
             ShaderClockKHR = 5055,
             ShaderEnqueueAMDX = 5067,
             QuadControlKHR = 5087,
+            BFloat16TypeKHR = 5116,
+            BFloat16DotProductKHR = 5117,
+            BFloat16CooperativeMatrixKHR = 5118,
             SampleMaskOverrideCoverageNV = 5249,
             GeometryShaderPassthroughNV = 5251,
             ShaderViewportIndexLayerEXT = 5254,
@@ -1291,6 +1307,7 @@ namespace Spv
             ArithmeticFenceEXT = 6144,
             FPGAClusterAttributesV2INTEL = 6150,
             FPGAKernelAttributesv2INTEL = 6161,
+            TaskSequenceINTEL = 6162,
             FPMaxErrorINTEL = 6169,
             FPGALatencyControlINTEL = 6171,
             FPGAArgumentInterfacesINTEL = 6174,
@@ -1301,7 +1318,9 @@ namespace Spv
             Subgroup2DBlockTransformINTEL = 6229,
             Subgroup2DBlockTransposeINTEL = 6230,
             SubgroupMatrixMultiplyAccumulateINTEL = 6236,
+            TernaryBitwiseFunctionINTEL = 6241,
             GroupUniformArithmeticKHR = 6400,
+            TensorFloat32RoundingINTEL = 6425,
             MaskedGatherScatterINTEL = 6427,
             CacheControlsINTEL = 6441,
             RegisterLimitsINTEL = 6460,
@@ -1597,6 +1616,7 @@ namespace Spv
 
         [AllowDuplicates, CRepr] public enum FPEncoding
         {
+            BFloat16KHR = 0,
             Max = 0x7fffffff,
         }
 
@@ -2412,13 +2432,19 @@ namespace Spv
             OpControlBarrierArriveINTEL = 6142,
             OpControlBarrierWaitINTEL = 6143,
             OpArithmeticFenceEXT = 6145,
+            OpTaskSequenceCreateINTEL = 6163,
+            OpTaskSequenceAsyncINTEL = 6164,
+            OpTaskSequenceGetINTEL = 6165,
+            OpTaskSequenceReleaseINTEL = 6166,
+            OpTypeTaskSequenceINTEL = 6199,
             OpSubgroupBlockPrefetchINTEL = 6221,
             OpSubgroup2DBlockLoadINTEL = 6231,
             OpSubgroup2DBlockLoadTransformINTEL = 6232,
             OpSubgroup2DBlockLoadTransposeINTEL = 6233,
             OpSubgroup2DBlockPrefetchINTEL = 6234,
             OpSubgroup2DBlockStoreINTEL = 6235,
             OpSubgroupMatrixMultiplyAccumulateINTEL = 6237,
+            OpBitwiseFunctionINTEL = 6242,
             OpGroupIMulKHR = 6401,
             OpGroupFMulKHR = 6402,
             OpGroupBitwiseAndKHR = 6403,
@@ -2427,6 +2453,7 @@ namespace Spv
             OpGroupLogicalAndKHR = 6406,
             OpGroupLogicalOrKHR = 6407,
             OpGroupLogicalXorKHR = 6408,
+            OpRoundFToTF32INTEL = 6426,
             OpMaskedGatherINTEL = 6428,
             OpMaskedScatterINTEL = 6429,
             Max = 0x7fffffff,