Redundancy backport #812
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Redundancy backport #812
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Top-Block Swap mode of Intel PCH allows to swap the boot block with
another location placed directly below it by redirecting the memory
accesses.
The range of the addresses to be redirected is configured using the Top
Swap Block Size (or BOOT_BLOCK_SIZE) PCH strap using 3 bits to encode
one of 8 sizes:
64 KB, 128 KB, 256 KB, 512 KB, 1 MB, 2 MB, 4 MB or 8 MB.
The source and target ranges depend on the configured size, eg:
- 64 KB - FFFF_0000h - FFFF_FFFFh -> FFFE_0000h - FFFE_FFFFh
- 128 KB - FFFE_0000h - FFFF_FFFFh -> FFFC_0000h - FFFD_FFFFh
- 8 MB - FF80_0000h - FFFF_FFFFh -> FF00_0000h - FF7F_FFFFh
Only supporting Alder Lake-P and Alder Lake-N for now.
Needed for the bootblock redundancy feature suggested at
https://mail.coreboot.org/archives/list/[email protected]/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/
TEST=check using xxd, MFIT tool, ensure VP6670 boots
Test details:
xxd:
./util/ifdtool/ifdtool -p adl -T 0x10000 vp66xx_fd.bin && \
xxd vp66xx_fd.bin > vp66xx.hex && \
xxd vp66xx_fd.bin.new > vp66xx_fd.new.hex && \
diff -au vp66xx_fd.hex vp66xx_fd.new.hex
File vp66xx_fd.bin is 4096 bytes
Writing new image to vp66xx_fd.bin.new
Change-Id: I7f2ae67808e8ac0aaa2a9ad5e091c2b358d4a5ab
--- vp66xx_fd.hex 2025-10-08 12:03:09.527193533 +0200
+++ vp66xx_fd.new.hex 2025-10-08 12:05:08.717108142 +0200
@@ -18,7 +18,7 @@
00000110: 7f78 0700 0000 0000 1800 0000 0000 1f00 .x..............
00000120: 0808 1170 0000 0000 0000 7f06 80f8 8107 ...p............
00000130: 0000 0000 0f00 0000 2222 2222 2202 2222 ........""""".""
-00000140: 0000 0000 0000 0000 0000 ff00 6000 80c8 ............`...
+00000140: 0000 0000 0000 0000 0000 ff00 0000 80c8 ................
00000150: 4586 0036 0000 0000 0002 5800 0000 4000 E..6......X...@.
00000160: 0018 0000 0000 0000 0000 0000 0000 0000 ................
00000170: 0000 0000 0000 0000 54b3 04a0 3000 0140 ........T...0..@
mfittool:
./mfit --gui -decompose protectli_vp66xx_v0.9.2.rom
In the UI:
Flash Settings > BIOS Configuration > Top Swap Block Size
shows the value changing to the expected one, ie.
-T 0x10000 results in 64kB
-T 0x20000 results in 128kB
-T 0x400000 results in 4MB
etc.
Change-Id: I50e9d4160ee4b60e83567bcd33c9d80d428cf2bb
Signed-off-by: Filip Gołaś <[email protected]>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89438
Reviewed-by: Sergii Dmytruk <[email protected]>
Tested-by: build bot (Jenkins) <[email protected]>
Allows ifittool to add FIT entries for files that are located in a different FMAP region than the FIT table. The region from where to source the file can be specified with -R. If not given it defaults to using the value of the mandatory -r, for full backwards compatibility. Example: Tested with a custom binary with the bootblock and corresponding FIT table in a separate region, and the microcode still in the COREBOOT region: λ ./ifittool -f test_ts.rom -a -n cpu_microcode_blob.bin -t 1 \ -r BOOTBLOCK \ -R COREBOOT \ -s 4 Change-Id: I7e49247f280ec118e09cf173795d7602a4c0d7f6 Signed-off-by: Filip Lewiński <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89608 Reviewed-by: Sergii Dmytruk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
To modify the Top Swap Block Size in the FD (if provided and CONFIG_HAVE_IFD_BIN=y), set the following Kconfig variables: - CONFIG_INTEL_HAS_TOP_SWAP - CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK - CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE - CONFIG_INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE Needed for the bootblock redundancy feature suggested at https://mail.coreboot.org/archives/list/[email protected]/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/ TEST=build VP66xx with custom Kconfig, check if TSBS is modified in FD Change-Id: I94d3d3e2511a7e56392a9e34f845ae91602ce7f1 Signed-off-by: Filip Gołaś <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89493 Reviewed-by: Sergii Dmytruk <[email protected]> Tested-by: build bot (Jenkins) <[email protected]>
Add Kconfig INTEL_TOP_SWAP_SEPARATE_REGIONS. When enabled, place the regular bootblock in BOOTBLOCK and the Top Swap bootblock in TOPSWAP to simplify A B updates. This lays groundwork for redundancy where one bootblock remains a read only golden copy and the other is replaceable. No swap control logic is added in this change. The option depends on INTEL_ADD_TOP_SWAP_BOOTBLOCK and defaults to n so existing builds are unchanged. A custom .fmd is required with BOOTBLOCK and TOPSWAP added at the end of the image. Background and update flow are described here: Link: https://mail.coreboot.org/archives/list/[email protected]/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5Y V35/ TEST=Build and run Protectli VP6650 (ADL-P), boots successfully with correct microcode Change-Id: I489406dd8d08ad85bb46324d3d009acb49b6c52a Signed-off-by: Filip Lewiński <[email protected]> Reviewed-on: https://review.coreboot.org/c/coreboot/+/89570 Tested-by: build bot (Jenkins) <[email protected]> Reviewed-by: Sergii Dmytruk <[email protected]>
Change-Id: Iad2722b474b0919d60731dbe2df6e9b571927c30 Signed-off-by: Filip Lewiński <[email protected]>
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Toggle the RTC BUC control bit for Top Swap bootblock selection based on the "attempt_slot_b" flag CMOS option, allowing to select which of the BOOTBLOCK or TOP_SWAP regions to boot from. This means that after an update, the CMOS option can be set to boot from the newer TOP_SWAP bootblock. In case of failure, CMOS can be cleared to revert to the known-good base BOOTBLOCK. This is part of ongoing implementation of a redundancy feature proposed on the mailing list: https://mail.coreboot.org/archives/list/[email protected]/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/ Switching between identical bootblocks doesn't impact further boot flow, i.e. selecting which FMAP region to load consecutive stages from. That is to be enabled in following patches. So far tested and enabled for the Alder Lake SoC. TEST=Boot VP6650, setting the attempt_slot_b flag to different values, observing that it resets/continues booting correctly. Change-Id: Ib183a1f72ee8585b2c4ad4376344de33ff54cbb9 Signed-off-by: Filip Lewiński <[email protected]>
…anism If the Top Swap mechanism is enabled, after running the bootblock from the TOP_SWAP region, boot from an updatable COREBOOT_TS FMAP region. Having flashed the TOP_SWAP bootblock and COREBOOT_TS, this allows the user to boot a newer version of the firmware with the ability to revert to the previous known-good version by performing a CMOS reset. Requires having a read-write COREBOOT_TS region in the FMAP file. This is part of an ongoing implementation of a redundancy feature proposed on the mailing list: https://mail.coreboot.org/archives/list/[email protected]/thread/C6JN2PB7K7D67EG7OIKB6BBERZU5YV35/ TEST=Boot Protectli VP6650, setting the attempt_slot_b flag to different values, observing the "Booting from COREBOOT/COREBOOT_TS region" prints correspondingly. Change-Id: Ieadc9bfbe940cbec79eb84f16a5d622bfbb82ede Signed-off-by: Filip Lewiński <[email protected]>
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Change-Id: Ib183a1f72ee8585b2c4ad4376344de33ff54cbb9 Signed-off-by: Filip Lewiński <[email protected]>
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Signed-off-by: Filip Lewiński <[email protected]>
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Backporting the entire upstream redundancy path train to our fork, merged ones as well as WIP
So far targeting only VP66XX