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## Current status
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* [ Design & verification stage] ( ../../../README.md )
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* [ HW development stages] ( ../../../../doc/project_governance/development_stages.md )
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- * [ Simulation results] ( https://reports.opentitan.org/hw/ip/aes/dv/latest/report.html )
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+ * [ Simulation results for Masked AES] ( https://reports.opentitan.org/hw/ip/aes_masked/dv/latest/report.html )
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+ * [ Simulation results for Unmasked AES] ( https://reports.opentitan.org/hw/ip/aes_unmasked/dv/latest/report.html )
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## Design features
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For detailed information on AES design features, please see the [ AES HWIP Technical Specification] ( ../README.md ) .
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## Current status
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* [ Design & verification stage] ( ../../../README.md )
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* [ HW development stages] ( ../../../../doc/project_governance/development_stages.md )
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- * [ Simulation results] ( https://reports.opentitan.org/hw/ip/kmac/dv/latest/report.html )
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+ * [ Simulation results for Masked KMAC] ( https://reports.opentitan.org/hw/ip/kmac_masked/dv/latest/report.html )
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+ * [ Simulation results for Unmasked KMAC] ( https://reports.opentitan.org/hw/ip/kmac_unmasked/dv/latest/report.html )
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## Design features
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For detailed information on KMAC design features, please see the [ KMAC HWIP technical specification] ( ../README.md ) .
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## Current status
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* [ Design & verification stage] ( ../../../README.md )
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* [ HW development stages] ( ../../../../doc/project_governance/development_stages.md )
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- * [ Simulation results] ( https://reports.opentitan.org/hw/ip/sram_ctrl/dv/latest/report.html )
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+ * [ Simulation results for SRAM] ( https://reports.opentitan.org/hw/ip/sram_ctrl_main/dv/latest/report.html )
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+ * [ Simulation results for retention SRAM] ( https://reports.opentitan.org/hw/ip/sram_ctrl_ret/dv/latest/report.html )
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## Design features
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For detailed information on SRAM_CTRL design features, please see the [ SRAM_CTRL HWIP technical specification] ( ../README.md ) .
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