aarch64: Extend iterator support for partial SVE FP modes

Define new iterators for partial floating-point modes, and cover these
in some existing mode_attrs.  This patch serves as a starting point for
an effort to extend support for unpacked floating-point operations.

To differentiate between BFloat mode iterators that need to test
TARGET_SSVE_B16B16, and those that don't (see LOGICALF), this patch
enforces the following naming convention:
	- _BF: BF16 modes will not test TARGET_SSVE_B16B16.
	- _B16B16: BF16 modes will test TARGET_SSVE_B16B16.

gcc/ChangeLog:

	* config/aarch64/aarch64-sve.md: Replace uses of SVE_FULL_F_BF
	with SVE_FULL_F_B16B16.
	Replace use of SVE_F with SVE_F_BF.
	* config/aarch64/iterators.md (SVE_PARTIAL_F): New iterator for
	partial SVE FP modes.
	(SVE_FULL_F_BF): Rename to SVE_FULL_F_B16B16.
	(SVE_PARTIAL_F_B16B16): New iterator (BF16 included) for partial
	SVE FP modes.
	(SVE_F_B16B16): New iterator for all SVE FP modes.
	(SVE_BF): New iterator for all SVE BF16 modes.
	(SVE_F): Redefine to exclude BF16 modes.
	(SVE_F_BF): New iterator to replace the previous SVE_F.
	(VPRED): Describe the VPRED mapping for partial vector modes.
	(b): Cover partial FP modes.
	(is_bf16): Likewise.

Author: SpencerAbson