Made the verilog module consistent with the Circuit simulation logic (#619)

* made the verilog module consistent with the simulation logic

* fixed logic

Author: 092vk

src/simulator/src/sequential/DflipFlop.js

@@ -135,17 +135,18 @@ export default class DflipFlop extends CircuitElement {
 module DflipFlop(q, q_inv, clk, d, a_rst, pre, en);
     parameter WIDTH = 1;
     output reg [WIDTH-1:0] q, q_inv;
-    input clk, a_rst, pre, en;
-    input [WIDTH-1:0] d;
+    input clk, a_rst, en;
+    input [WIDTH-1:0] d, pre;
 
-    always @ (posedge clk or posedge a_rst)
-    if (a_rst) begin
-        q <= 'b0;
-        q_inv <= 'b1;
-    end else if (en == 0) ;
-    else begin
-        q <= d;
-        q_inv <= ~d;
+    always @ (posedge clk or posedge a_rst) begin
+        if (a_rst) begin
+            q <= pre;
+            q_inv <= ~pre;
+        end else if (en) begin
+            q <= d;
+            q_inv <= ~d;
+        end
+        // When en == 0, hold current state
     end
 endmodule
     `