Support for M68K CPU

[raminsadre]

(I hope this is the right place to ask. I didn't find a community forum)

Hi,
I would like to use Boomerang on binaries for the Motorola 680x0 CPU series. I have already written a loader. That was the easy part. Now the decoder...
Some questions related to this:

1. (Just in case, one can hope:) Has anybody already written a decoder or a SSL specification for M68K?
2. For the lifting: It's not 100% clear to me what belongs in the SSL file and what belongs in the decoder class. Do I understand correctly that most of the semantic is defined in the SSL file and the code in the decoder just handles the cases that need extra care?
3. M68K has an adressing mode where the base register is incremented after (resp. decremented before) the operation, for example "add d0, (a1)+". My plan is to handle this like a normal indirect address (e.g. "add d0, (a1)") in the SSL file and add the extra effect (increment register %a1) manually in the liftInstruction method. Correct?
4. M68K has an instruction that can move multiple registers in one go, for example the instruction "movem d0/d2/d7, -(a1)" would move the three data registers d0, d2 and d7. Do I understand correctly that this cannot be expressed in SSL and should be manually implemented in the liftInstruction method of the decoder?

Thanks for any help and pointers (expect null pointers, haha)

[ceeac]

1. See commit d654bf4, though you probably need to rewrite it because the syntax has changed in the meantime. You will need to write both a decoder plugin and a frontend plugin (Though the frontend can probably be a stub, at least initially; I do not have experience with M68K) and then use them in Project::createFrontEnd().
2. Yes.
3. You can try to "undo" the memof of the second operand with an a[ ], otherwise yes.
4. You can overload the instruction template with a different number of parameters. (see for example the blt instruction template in ppc.ssl).