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Mips Tracewrap Support Initialize
1 parent ab90d00 commit 46810c4

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4 files changed

+191
-43
lines changed

4 files changed

+191
-43
lines changed

‎linux-user/mips/trace_info.h

+6-1
Original file line numberDiff line numberDiff line change
@@ -2,5 +2,10 @@
22

33
#include "frame_arch.h"
44

5+
#if defined(TARGET_MIPS)
56
const uint64_t frame_arch = frame_arch_mips;
6-
const uint64_t frame_mach = frame_mach_mipsisa32 ;
7+
const uint64_t frame_mach = frame_mach_mipsisa32;
8+
#else
9+
const uint64_t frame_arch = frame_arch_mips64;
10+
const uint64_t frame_mach = frame_mach_mipsisa64;
11+
#endif

‎target/mips/helper.h

+11-5
Original file line numberDiff line numberDiff line change
@@ -19,11 +19,17 @@ DEF_HELPER_3(lld, tl, env, tl, int)
1919
#ifdef HAS_TRACEWRAP
2020
DEF_HELPER_1(trace_newframe, void, tl)
2121
DEF_HELPER_3(trace_endframe, void, env, tl, i32)
22-
DEF_HELPER_2(trace_load_reg, void, i32, i32)
23-
DEF_HELPER_2(trace_store_reg, void, i32, i32)
24-
DEF_HELPER_3(trace_ld, void, env, i32, i32)
25-
DEF_HELPER_3(trace_st, void, env, i32, i32)
26-
#endif //HAS_TRACEWRAP
22+
DEF_HELPER_2(trace_load_reg32, void, i32, i32)
23+
DEF_HELPER_2(trace_store_reg32, void, i32, i32)
24+
DEF_HELPER_3(trace_load_mem32, void, env, i32, i32)
25+
DEF_HELPER_3(trace_store_mem32, void, env, i32, i32)
26+
#ifdef TARGET_MIPS64
27+
DEF_HELPER_2(trace_load_reg64, void, i32, i64)
28+
DEF_HELPER_2(trace_store_reg64, void, i32, i64)
29+
DEF_HELPER_2(trace_load_mem64, void, i32, i64)
30+
DEF_HELPER_2(trace_store_mem64, void, i32, i64)
31+
#endif // TARGET_MIPS64
32+
#endif // HAS_TRACEWRAP
2733

2834
DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl)
2935
#ifdef TARGET_MIPS64

‎target/mips/tcg/translate.c

+99-5
Original file line numberDiff line numberDiff line change
@@ -1224,6 +1224,73 @@ static const char regnames_LO[][4] = {
12241224
"LO0", "LO1", "LO2", "LO3",
12251225
};
12261226

1227+
/*
1228+
** Include useful headers and defines
1229+
*/
1230+
#ifdef HAS_TRACEWRAP
1231+
#include <frame_arch.h>
1232+
#endif // HAS_TRACEWRAP
1233+
1234+
static inline void gen_trace_newframe(uint64_t pc) {
1235+
#ifdef HAS_TRACEWRAP
1236+
1237+
// create new traceframe
1238+
TCGv_i64 _pc = tcg_const_i64(pc);
1239+
gen_helper_trace_newframe(_pc);
1240+
tcg_temp_free_i64(_pc);
1241+
1242+
// get machine type
1243+
#ifdef TARGET_MIPS64
1244+
TCGv_ptr mt = tcg_const_ptr(FRAME_MODE_MIPS64); // TODO: Check this
1245+
#else
1246+
TCGv_ptr mt = tcg_const_ptr(FRAME_MODE_MIPS);
1247+
#endif // TARGET_MIPS64
1248+
1249+
// set trace mode to mips64 or mips
1250+
gen_helper_trace_mode(mt);
1251+
tcg_trace_free_ptr(mt);
1252+
1253+
#endif // HAS_TRACEWRAP
1254+
}
1255+
1256+
static inline void gen_trace_endframe(uint64_t pc) {
1257+
#ifdef HAS_TRACEWRAP
1258+
TCGv_i64 _pc = tcg_const_i64(pc);
1259+
gen_helper_trace_endframe(cpu_env, _pc);
1260+
tcg_temp_free_i64(_pc);
1261+
1262+
#endif // HAS_TRACEWRAP
1263+
}
1264+
1265+
static void gen_trace_load_reg(int reg, TCGv var) {
1266+
#ifdef HAS_TRACEWRAP
1267+
1268+
TCGv_i32 r = tcg_const_i32(reg);
1269+
#ifdef TARGET_MIPS64
1270+
gen_helper_trace_load_reg64(r, var);
1271+
#else
1272+
gen_helper_trace_load_reg(r, var);
1273+
#endif
1274+
tcg_temp_free_i32(r);
1275+
1276+
#endif // HAS_TRACEWRAP
1277+
}
1278+
1279+
static void gen_trace_store_reg(int reg, TCGv var) {
1280+
#ifdef HAS_TRACEWRAP
1281+
1282+
TCGv_i32 r = tcg_const_i32(reg);
1283+
#ifdef TARGET_PPC64
1284+
gen_helper_trace_store_reg64(r, var);
1285+
#else
1286+
gen_helper_trace_store_reg(r, var);
1287+
#endif
1288+
tcg_temp_free_i32(r);
1289+
1290+
#endif // HAS_TRACEWRAP
1291+
}
1292+
1293+
12271294
/* General purpose registers moves. */
12281295
void gen_load_gpr(TCGv t, int reg)
12291296
{
@@ -1232,13 +1299,17 @@ void gen_load_gpr(TCGv t, int reg)
12321299
} else {
12331300
tcg_gen_mov_tl(t, cpu_gpr[reg]);
12341301
}
1302+
1303+
gen_trace_load_reg(reg, t);
12351304
}
12361305

12371306
void gen_store_gpr(TCGv t, int reg)
12381307
{
12391308
if (reg != 0) {
12401309
tcg_gen_mov_tl(cpu_gpr[reg], t);
12411310
}
1311+
1312+
gen_trace_store_reg(reg, t);
12421313
}
12431314

12441315
#if defined(TARGET_MIPS64)
@@ -1249,13 +1320,21 @@ void gen_load_gpr_hi(TCGv_i64 t, int reg)
12491320
} else {
12501321
tcg_gen_mov_i64(t, cpu_gpr_hi[reg]);
12511322
}
1323+
1324+
#ifdef HAS_TRACEWRAP
1325+
gen_trace_load_reg(reg, t);
1326+
#endif
12521327
}
12531328

12541329
void gen_store_gpr_hi(TCGv_i64 t, int reg)
12551330
{
12561331
if (reg != 0) {
12571332
tcg_gen_mov_i64(cpu_gpr_hi[reg], t);
12581333
}
1334+
1335+
#ifdef HAS_TRACEWRAP
1336+
gen_trace_store_reg(reg, t);
1337+
#endif
12591338
}
12601339
#endif /* TARGET_MIPS64 */
12611340

@@ -1264,6 +1343,7 @@ static inline void gen_load_srsgpr(int from, int to)
12641343
{
12651344
TCGv t0 = tcg_temp_new();
12661345

1346+
// if from == r0 then just move 0
12671347
if (from == 0) {
12681348
tcg_gen_movi_tl(t0, 0);
12691349
} else {
@@ -1283,6 +1363,8 @@ static inline void gen_load_srsgpr(int from, int to)
12831363
}
12841364
gen_store_gpr(t0, to);
12851365
tcg_temp_free(t0);
1366+
1367+
#ifdef H
12861368
}
12871369

12881370
static inline void gen_store_srsgpr(int from, int to)
@@ -16033,19 +16115,24 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
1603316115
int insn_bytes;
1603416116
int is_slot;
1603516117

16118+
// get pc_next and start generating new traceframe
16119+
uint64_t pc_next = ctx->base.px_next;
16120+
gen_trace_newframe(pc_next);
16121+
16122+
// translate depending on architecture
1603616123
is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
1603716124
if (ctx->insn_flags & ISA_NANOMIPS32) {
16038-
ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
16125+
ctx->opcode = translator_lduw(env, &ctx->base, pc_next);
1603916126
insn_bytes = decode_isa_nanomips(env, ctx);
1604016127
} else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
16041-
ctx->opcode = translator_ldl(env, &ctx->base, ctx->base.pc_next);
16128+
ctx->opcode = translator_ldl(env, &ctx->base, pc_next);
1604216129
insn_bytes = 4;
1604316130
decode_opc(env, ctx);
1604416131
} else if (ctx->insn_flags & ASE_MICROMIPS) {
16045-
ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
16132+
ctx->opcode = translator_lduw(env, &ctx->base, pc_next);
1604616133
insn_bytes = decode_isa_micromips(env, ctx);
1604716134
} else if (ctx->insn_flags & ASE_MIPS16) {
16048-
ctx->opcode = translator_lduw(env, &ctx->base, ctx->base.pc_next);
16135+
ctx->opcode = translator_lduw(env, &ctx->base, pc_next);
1604916136
insn_bytes = decode_ase_mips16e(env, ctx);
1605016137
} else {
1605116138
gen_reserved_instruction(ctx);
@@ -16074,7 +16161,11 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
1607416161
if (is_slot) {
1607516162
gen_branch(ctx, insn_bytes);
1607616163
}
16164+
16165+
// update pc for next instruction
16166+
// and get pc_next
1607716167
ctx->base.pc_next += insn_bytes;
16168+
pc_next = ctx->base.pc_next;
1607816169

1607916170
if (ctx->base.is_jmp != DISAS_NEXT) {
1608016171
return;
@@ -16085,10 +16176,13 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
1608516176
* See mips_tr_init_disas_context about single-stepping a branch
1608616177
* together with its delay slot.
1608716178
*/
16088-
if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
16179+
if (pc_next - ctx->page_start >= TARGET_PAGE_SIZE
1608916180
&& !ctx->base.singlestep_enabled) {
1609016181
ctx->base.is_jmp = DISAS_TOO_MANY;
1609116182
}
16183+
16184+
// end the frame
16185+
gen_pc_endframe(pc_next);
1609216186
}
1609316187

1609416188
static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)

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