Merge pull request #15453 from MaximIntegrated/fix-spi_glitch

0xc0170 · web-flow · commit 7049bfcef405 · 2023-09-13T13:24:35.000+01:00
Fix MAX32660, MAX32670 SPI glitch fix
diff --git a/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32660/Libraries/PeriphDrivers/Source/SPI/spi_reva.c
@@ -764,7 +764,7 @@ int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req)
     states[spi_num].started = 0;
     states[spi_num].req_done = 0;
     // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive).
-    if (states[spi_num].ssDeassert == 1) {
+    if (states[spi_num].drv_ssel && (states[spi_num].ssDeassert == 1)) {
         (req->spi)->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN);
     }
 
diff --git a/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c b/targets/TARGET_Maxim/TARGET_MAX32670/Libraries/PeriphDrivers/Source/SPI/spi_reva.c
@@ -764,7 +764,7 @@ int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req)
     states[spi_num].started = 0;
     states[spi_num].req_done = 0;
     // HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive).
-    if (states[spi_num].ssDeassert == 1) {
+    if (states[spi_num].drv_ssel && (states[spi_num].ssDeassert == 1) ) {
         (req->spi)->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN);
     }
 

Original file line number	Diff line number	Diff line change
`@@ -764,7 +764,7 @@ int MXC_SPI_RevA_TransSetup(mxc_spi_reva_req_t *req)`
`764`	`764`	`states[spi_num].started = 0;`
`765`	`765`	`states[spi_num].req_done = 0;`
`766`	`766`	`// HW requires disabling/renabling SPI block at end of each transaction (when SS is inactive).`
`767`		`- if (states[spi_num].ssDeassert == 1) {`
	`767`	`+ if (states[spi_num].drv_ssel && (states[spi_num].ssDeassert == 1)) {`
`768`	`768`	`(req->spi)->ctrl0 &= ~(MXC_F_SPI_REVA_CTRL0_EN);`
`769`	`769`	`}`
`770`	`770`